Embedded processor architecture with shared memory with design under test
AssigneeCadence Design Systems, Inc.
InventorsMitchell G. Poplack, Christopher Coffman, Hitesh Gannu
Life of this patent
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Abstract
A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the emulation data exchanged via the shared memory.
Claims18
An emulation system comprising:
- an emulation chip comprising a non-transitory storage medium, an emulation processor including a programmable device configured to emulate a portion of a design under test, and a simulation processor, the non-transitory storage medium is coupled directly to the emulation processor and to simulation processor and is partitioned into a first portion configured to store emulation data for the emulation processor and a second portion configured to store simulation data for the simulation processor;
- the simulation processor configured to:
- execute one or more simulation operations using one or more signals received from the emulation processor emulating the portion of the design under test;
- and
- write a simulation data record generated by executing the one or more simulation operations to the first portion of the non-transitory storage medium of the emulation chip;
- and
- the emulation processor further configured to:
- read the simulation data record from at least one of the first portion or the second portion of the non-transitory storage medium;
- update at least one emulation operation of the design under test based on the simulation data record;
- and
- based on the updated at least one emulation operation, write an emulation data record to the second portion of the non-transitory storage medium of the emulation chip.
An emulation method comprising:
- emulating, by an emulation processor included in an emulation chip, a portion of a design under test, wherein the emulation processor includes a programmable device;
- executing, by a simulation processor included in the emulation chip, one or more simulation operations using one or more signals received from the emulation processor emulating the portion of a design under test;
- writing, by the simulation processor to a non-transitory storage medium in the emulation chip, a simulation data record generated by executing the one or more simulation operations, the non-transitory storage medium is coupled directly to the emulation processor and to simulation processor and is partitioned into a first portion configured to store emulation data for the emulation processor and a second portion configured to store simulation data for the simulation processor;
- reading, by the emulation processor from at least one of the first portion or the second portion of the non-transitory storage medium, the simulation data record;
- updating, by the emulation processor, at least one emulation operation of the design under test based on the simulation data record;
- and
- based on the updated at least one emulation operation, writing an emulation data record to the second portion of the non-transitory storage medium of the emulation chip.
Dependencies are inferred from the claim text.