Controlling data allocation to storage circuitry

An apparatus comprising:

• control circuitry configured to control allocation of a given data item to storage circuitry and storage of the given data item to an intermediate buffer, wherein the intermediate buffer intermediates the storage circuitry and further storage circuitry arranged in a memory hierarchy;
• hit notification circuitry configured to receive a hit signal indicative of a lookup operation performed in the further storage circuitry resulting in a hit, the lookup operation indicating the given data item, wherein in response to the hit signal, the hit notification circuitry is configured to cause the control circuitry to store the given data item in the intermediate buffer;
• and
• mode control circuitry configured to change an operating mode of the control circuitry between an allocation mode and a non-allocation mode, wherein
• in the allocation mode, the control circuitry is configured to cause the allocation of the given data item from the intermediate buffer to the storage circuitry prior to causing the given data item to be deleted from the intermediate buffer;
• in the non-allocation mode, the control circuitry is configured to suppress the allocation of the given data item from the intermediate buffer to the storage circuitry, the apparatus further comprising:
• first prefetching circuitry configured to prefetch a future data item based on a predicted load operation and to store the future data item in the storage circuitry;
• and
• the mode control circuitry is configured to control the first prefetching circuitry based on the operating mode of the control circuitry, wherein
• in the allocation mode, the mode control circuitry is configured to enable the first prefetching circuitry;
• and
• in the non-allocation mode, the mode control circuitry is configured to disable the first prefetching circuitry.

A method comprising:

• controlling allocation of a given data item to storage circuitry and storage of the data item to an intermediate buffer, wherein the intermediate buffer intermediates the storage circuitry and further storage circuitry arranged in a memory hierarchy;
• receiving a hit signal indicative of a lookup operation performed in the further storage circuitry resulting in a hit, the lookup operation indicating the given data item, wherein in response to the hit signal, the given data item is stored in the intermediate buffer;
• and
• changing an operating mode between an allocation mode and a non-allocation mode, wherein
• in the allocation mode, the allocation of the given data item from the intermediate buffer to the storage circuitry occurs prior to causing the given data item to be deleted from the intermediate buffer;
• in the non-allocation mode, the allocation of the given data item from the intermediate buffer to the storage circuitry is suppressed;
• storing a cache line comprising a plurality of data items including the given data item and at least one further data item;
• counting a number of load operations indicating at least one of the plurality of data items;
• in response to the number of load operations being equal to a number of data items in the plurality of data items, deleting the cache line.

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• control circuitry configured to control allocation of a given data item to storage circuitry and storage of the given data item to an intermediate buffer, wherein the intermediate buffer intermediates the storage circuitry and further storage circuitry arranged in a memory hierarchy;
• hit notification circuitry configured to receive a hit signal indicative of a lookup operation performed in the further storage circuitry resulting in a hit, the lookup operation indicating the given data item, wherein in response to the hit signal, the hit notification circuitry is configured to cause the control circuitry to store the given data item in the intermediate buffer;
• and
• mode control circuitry configured to change an operating mode of the control circuitry between an allocation mode and a non-allocation mode, wherein
• in the allocation mode, the control circuitry is configured to cause the allocation of the given data item from the intermediate buffer to the storage circuitry prior to causing the given data item to be deleted from the intermediate buffer;
• in the non-allocation mode, the control circuitry is configured to suppress the allocation of the given data item from the intermediate buffer to the storage circuitry;
• the intermediate buffer comprises a line fill buffer;
• a cache comprises the storage circuitry and the intermediate buffer;
• the line fill buffer is configured to store a cache line comprising a plurality of data items;
• the plurality of data items including the given data item and at least one further data item;
• the apparatus comprises load count circuitry configured to count a number of load operations indicating at least one of the plurality of data items;
• and
• in response to the number of load operations being equal to a number of data items in the plurality of data items, the load count circuitry causes the line fill buffer to delete the cache line.