Address-range memory mirroring in a computer system, and related methods

A method of performing address range memory mirroring in a computer system, comprising:

• receiving a write request comprising a write memory address and write data;
• determining if the write memory address of the write request is within a memory address range stored in any of one or more mirror address range registers each configured to store a memory address range;
• communicating the write data of the write request to a first memory channel mapped as a primary memory channel to the write memory address, to be written as primary write data to at least one memory chip coupled to the first memory channel;
• and
• in response to determining the write memory address of the write request is within a memory address range stored in any of the one or more mirror address range registers:
• communicating the write data of the write request to a second memory channel mapped as a secondary memory channel to the write memory address, to be written as redundant write data to at least one memory chip coupled to the second memory channel;
• detecting an error in the first memory channel;
• and
• in response to detection of the error in the first memory channel;
• not communicating next write data of a next write request comprising the next write data and a next write memory address to the first memory channel;
• and
• communicating the next write data of the write request to the second memory channel to be written as write data to at least one memory chip coupled to the second memory channel;
• and
• in response to the error in the first memory channel being resolved:
• not communicating the write data to the second memory channel;
• and
• communicating the write data of the write request to the first memory channel, to be written as write data to at least one memory chip coupled to the second memory channel.

A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to:

• receive a write request from a central processing unit (CPU), the write request comprising a write memory address and write data;
• determine if the write memory address of the write request is within a memory address range stored in any of one or more mirror address range registers each configured to store a memory address range;
• communicate the write data of the write request to a first memory channel mapped as a primary memory channel to the write memory address, to be written as primary write data to at least one memory chip coupled to the first memory channel;
• and
• in response to determining the write memory address of the write request is within a memory address range stored in any of the one or more mirror address range registers:
• communicate the write data of the write request to a second memory channel mapped as a secondary memory channel to the write memory address, to be written as redundant write data to at least one memory chip coupled to the second memory channel;
• detecting an error in the first memory channel;
• and
• in response to detection of the error in the first memory channel:
• not communicating next write data of a next write request comprising the next write data and a next write memory address to the first memory channel;
• and
• communicating the next write data of the write request to the second memory channel to be written as write data to at least one memory chip coupled to the second memory channel;
• and
• in response to the error in the first memory channel being resolved:
• not communicate the write data to the second memory channel;
• and
• communicate the write data of the write request to the first memory channel, to be written as write data to at least one memory chip coupled to the second memory channel.

A computer system, comprising:

• one or more mirror address range registers each configured to store a memory address range;
• a memory controller unit (MCU) system comprising a memory control circuit (MCC) comprising:
• a first memory channel;
• a second memory channel;
• and
• an external MCC interface coupled to the first memory channel and the second memory channel;
• a memory mirror agent coupled between a network coupled to a central processing unit (CPU) and the external MCC interface of the MCC, the memory mirror agent configured to:
• receive a write request comprising a write memory address and write data over the network;
• determine if the write memory address of the write request is within a memory address range stored in any of the one or more mirror address range registers;
• communicate the write data of the write request through the external MCC interface to a first memory channel mapped as a primary memory channel to the write memory address, to be written as primary write data to at least one memory chip coupled to the first memory channel;
• and
• in response to determining the write memory address of the write request is within the memory address range stored in any of the one or more mirror address range registers:
• communicate the write data of the write request to a second memory channel mapped as a secondary memory channel to the write memory address, to be written as redundant write data to at least one memory chip coupled to the second memory channel.