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US 12,182,416 B2Granted
Memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJung Min You, Seong-Jin Cho
Life of this patent
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Abstract
According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.
Claims14
A memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a control logic including a mode register, the control logic configured to:
- perform a first refresh operation in response to a first refresh command,
- generate an internal mode register write command in response to the first refresh command in a first mode,
- in the first mode, write a bank address and a row address, on which the first refresh operation is performed, to the mode register in response to the internal mode register write command, and
- perform a second refresh operation in response to a second refresh command in a second mode different from the first mode, wherein:
- the internal mode register write command includes a first internal mode register write command and a second internal mode register write command,
- the mode register includes a first mode register and a second mode register, and
- the control logic is configured to write the bank address to the first mode register in response to the first internal mode register write command, and write the row address to the second mode register in response to the second internal mode register write command.
7 more elements
A memory system, comprising:
- a memory controller configured to generate a refresh command;
- and
- a memory device which includes a memory cell array and a control logic, the memory cell array including a plurality of memory cells, the control logic including a mode register and configured to perform a refresh operation in response to the refresh command,
- wherein the memory device is configured to:
- store a bank address and a row address, on which the refresh operation is performed, in the mode register, and
- output the bank address and the row address from the mode register to the memory controller outside the memory device in response to a mode register read command received from the memory controller,
- wherein, in a first mode, the control logic is configured to store the bank address and the row address in the mode register in response to the refresh command,
- wherein the mode register read command includes first and second mode register read commands, and
- wherein the memory device is configured to output one of the bank address and the row address to the memory controller in response to the first mode register read command and output the other of the bank address and the row address to the memory controller in response to the second mode register read command.
6 more elements
A memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a control logic including a mode register, wherein:
- the control logic is configured to:
- receive a first refresh command and a second refresh command after receiving the first refresh command,
- perform a first refresh operation in response to the first refresh command, and a second refresh operation in response to the second refresh command,
- store a first bank address and a first row address, on which the first refresh operation is performed, in the mode register in response to the first refresh command,
- store a second bank address and a second row address, on which the second refresh operation is performed, in the mode register in response to the second refresh command,
- output the first bank address and the first row address from the mode register to an outside of the memory device in response to a first mode register read command from the outside of the memory device in at least a portion of a period in which the first refresh operation is performed by receiving the first refresh command, and
- output a second bank address and a second row address to the outside of the memory device from the mode register in response to a second mode register read command from the outside of the memory device in at least a portion of a period in which the second refresh operation is performed by receiving the second refresh command,
- the second bank address is different from the first bank address, and
- the second row address is different from the first row address.
9 more elements
Dependencies are inferred from the claim text.