Integrated circuit protection against reverse engineering

An integrated circuit, comprising:

• a first clocked memory element having a first data input, a first data output and a first clock input;
• a second clocked memory element having a second data input, a second data output and a second clock input;
• a logic path coupling the first data output to the second data input;
• a clock signal line coupling the first clock input to the second clock input;
• wherein delays of the logic path and the clock signal line are such that
• a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by the second clocked memory element with the same clock edge of the clock signal,
• or
• a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal;
• a secret bit generation circuit configured to output a secret bit whose value depends on whether
• a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by the second clocked memory element with the same clock edge of the clock signal,
• or
• a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal;
• and
• a processing circuit configured to at least one of
• check whether the value of the secret bit is correct and, if the value of the secret bit is not correct, signal an alarm,
• and
• use the secret bit as a bit of cryptographic key and perform a cryptographic operation using the cryptographic key.