Control channel architecture

A multi-processor system-on-chip, comprising:

• an execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip resources;
• a first control point processor that is physically and programmatically independent from the execution domain processor and configured to generate a first runtime isolation control data stream for controlling access by the first execution domain to the one or more system-on-chip resources by identifying at least a first system-on-chip resource that the first execution domain is allowed to access;
• an access control circuit connected between the first execution domain and the one or more system-on-chip resources, comprising:
• a programmable front end which is connected and configured to receive the first runtime isolation control data stream from the first control point processor, and
• a signals-based back end which is connected and configured to provide a dynamic runtime isolation barrier in response to the first runtime isolation control data stream, thereby controlling access to the one or more system-on-chip resources by the first execution domain, wherein the signals-based back end comprises access control channel hardware and software which provides the dynamic runtime isolation barrier to control system-on-chip resource signals going to and coming from the first execution domain in response to the first runtime isolation control data stream, the access control channel hardware and software comprising:
• a JTAG debug control block which is programmed by the first runtime isolation control data stream to selectively enable or disable a scan chain control signal going into the execution domain processor on a per-partition basis, thereby providing dynamic partition-based JTAG debug control for isolating software partitions across JTAG debug operations.

A multi-processor system-on-chip, comprising:

• an execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip resources;
• a first control point processor that is physically and programmatically independent from the execution domain processor and configured to generate a first runtime isolation control data stream for controlling access by the first execution domain to the one or more system-on-chip resources by identifying at least a first system-on-chip resource that the first execution domain is allowed to access;
• an access control circuit connected between the first execution domain and the one or more system-on-chip resources, comprising:
• a programmable front end which is connected and configured to receive the first runtime isolation control data stream from the first control point processor, and
• a signals-based back end which is connected and configured to provide a dynamic runtime isolation barrier in response to the first runtime isolation control data stream, thereby controlling access to the one or more system-on-chip resources by the first execution domain, wherein the signals-based back end comprises access control channel hardware and software which provides the dynamic runtime isolation barrier to control system-on-chip resource signals going to and coming from the first execution domain in response to the first runtime isolation control data stream, the access control channel hardware and software comprising:
• a pre-emption control block which is programmed by the first runtime isolation control data stream to establish one or more pre-emption vector addresses in memory for different types of allowed pre-emption interrupt triggers so that the pre-emption control block determines if a received pre-emption interrupt request is allowed for the first execution domain before setting a pre-emption event line to the first execution domain.

A method for controlling operations of an execution domain on a multi-processor system-on-chip, comprising:

• generating a runtime isolation control data stream by a control point processor for controlling access to one or more system-on-chip resources by an execution domain processor, where the runtime isolation control data stream identifies at least a first system-on-chip resource that the execution domain processor is allowed to access and a second system-on-chip resource that the execution domain processor is not allowed to access;
• receiving the runtime isolation control data stream at a programmable front end of an access control circuit which is connected between the execution domain processor and the one or more system-on-chip resources;
• generating, at a signals-based back end of the access control circuit, a dynamic runtime isolation barrier in response to the runtime isolation control data stream, where the dynamic runtime isolation barrier controls access to the one or more system-on-chip resources by the execution domain processor that is physically and programmatically independent from the control point processor;
• running a first execution domain on the execution domain processor to access the one or more system-on-chip resources in compliance with the dynamic runtime isolation barrier;
• generating a second runtime isolation control data stream during runtime which reconfigures how access is controlled to the one or more system-on-chip resources by the first execution domain;
• receiving the second runtime isolation control data stream during runtime;
• generating, at the signals-based back end of the access control circuit, an updated dynamic runtime isolation barrier in response to the second runtime isolation control data stream which reconfigures how access is controlled to the one or more system-on-chip resources by the first execution domain processor;
• and
• running the first execution domain in compliance with the updated runtime isolation barrier without a reboot.

A system-on-chip comprising:

• an interconnect;
• one or more system-on-chip resources connected to the interconnect;
• a system-on-chip control point entity coupled to the interconnect and configured to generate a plurality of two-way control channel data streams;
• a plurality of execution domain processors that are not directly connected to the interconnect;
• and
• a plurality of access control channels attached, respectively, between the plurality of execution domain processors and the interconnect, where each access control channel that is attached to an execution domain comprises:
• a programmable front end which is connected and configured to receive a corresponding two-way control channel data stream from the system-on-chip control point entity, and
• a signals-based back end which is connected and configured to provide a dynamic runtime isolation barrier in response to the corresponding two-way control channel data stream, thereby controlling access to the one or more system-on-chip resources by the attached execution domain, wherein the signals-based back end at each access control channel that is attached to an execution domain comprises access control channel hardware and software which provides the dynamic runtime isolation barrier to control system-on-chip resource signals going to and coming from the attached execution domain in response to the corresponding two-way control channel data stream, the access control channel hardware and software comprising:
• a reset control block which is programmed by the corresponding two-way control channel data stream to establish one or more reset vector addresses in memory for different types of allowed resets so that the reset control block determines if a received reset request is a reset type that is allowed for the attached execution domain before setting a reset line to the attached execution domain.