Serial bus system and method

A secondary device comprising:

• a first port configured to be connected to a first port of a primary device;
• and
• a second port configured to be connected to a second port of the primary device, wherein:
• the first port of the secondary device is configured to receive a clock signal determining, for each bit transmission between the primary device and the secondary device, a succession of a first phase, a second phase, a third phase and a fourth phase;
• the secondary device is configured to put its second port in a high impedance state during the first, second and fourth phases of each bit transmission between the primary device and the secondary device;
• and
• the secondary device is configured, during the third phase of a data bit transmission from the secondary device to the primary device, to discharge its second port to a reference potential when a value of the data bit transmission from the secondary device to the primary device has a first value and to leave its second port in the high impedance state when the value of the data bit transmission from the secondary device to the primary device has a second value.

A method of transmitting a bit between a secondary device and a primary device, the secondary device comprising a first port connected to a first port of the primary device and a second port connected to a second port of the primary device, wherein:

• providing, by the primary device, a clock signal to the first port of the secondary device, the clock signal determining, for each bit transmission between the primary device and the secondary device, a succession of a first phase, a second phase, a third phase and a fourth phase;
• during the first phase of a data bit transmission between the primary device and the secondary device, loading the second port of the primary device to a first potential different from a reference potential;
• during the first phase of the data bit transmission between the primary device and the secondary device, leaving the second port of the secondary device in a high impedance state;
• during the second phase of the data bit transmission between the primary device and the secondary device, leaving the second port of the primary device in the high impedance state;
• during the third phase of a data bit transmission from the secondary device to the primary device, leaving the second port of the primary device in the high impedance state;
• and
• during the fourth phase of the data bit transmission between the primary device and the secondary device, determining a value for the data bit transmitted between the primary device and the secondary device based on a potential on the second port of the primary device and the second port of the secondary device.