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US 12,182,055 B1Granted
Power control logic using inter-chip
AssigneeAmazon Technologies, Inc.
InventorsLinfei Guo, Sagnik Kar
Life of this patent
Estimating the term…
Abstract
Systems and techniques for power delivery to an electronic device using multiple power management integrated circuits (PMICs) are described herein. The systems and techniques provide for two signal connections between each of the PMICs to sync transition signals on a first line and provide faults to interrupt operations on a second line. The PMICs are connected to an electronic device that commands power transitions for voltage rails from the PMICs with the commands received over I2C communication from the electronic device.
Claims20
A power management system for a device, comprising:
- a system on a chip (SoC) comprising a communication interface comprising a first communication pin and a second communication pin;
- a first power management integrated circuit (PMIC) coupled to the first communication pin through a first wire and coupled to the second communication pin through a second wire and configured to provide power to the SoC on a first plurality of voltage rails;
- and
- a second PMIC coupled to the first wire and the second wire and further coupled to the first PMIC through a unidirectional synchronization channel between the first PMIC and the second PMIC and a bidirectional fault channel between the first PMIC and the second PMIC, the bidirectional fault channel configured for asynchronous signaling of fault events, and the second PMIC configured to provide power to the SoC on a second plurality of voltage rails, wherein:
- the SoC sends, via the first communication pin, a first signal to the first PMIC, the first signal causing a change in a power state of one or more of the first or the second plurality of voltage rails;
- and
- the first PMIC sends, via the unidirectional synchronization channel and based on the first signal, a second signal to the second PMIC, the second signal causing the second PMIC to sync the change in the power state.
4 more elements
A method, comprising:
- receiving, by a first power management integrated circuit (PMIC) coupled with a system on a chip (SoC) through a first wire coupled to a first communication pin of a first communication connection, a command from the SoC, the command causing a change in a power state of one or more voltage rails provided to the SoC from the first PMIC and a second PMIC, wherein:
- the first PMIC is further coupled with the SoC through a second wire coupled to a second communication pin of the first communication connection, and
- the second PMIC is coupled to the first wire and the second wire and further coupled to the first PMIC through a second communication connection comprising a unidirectional synchronization channel between the first PMIC and the second PMIC and a bidirectional fault channel between the first PMIC and the second PMIC;
- syncing, through the unidirectional synchronization channel, the command causing the change in the power state of the one or more voltage rails of the SoC;
- causing, in response to syncing the command, the first PMIC or the second PMIC to change the power state of the one or more voltage rails;
- and
- sending a message to the SoC confirming the change of the power state.
4 more elements
A system, comprising:
- a system on a chip (SoC) comprising a first communication pin and a second communication pin;
- a first power management integrated circuit (PMIC) coupled to the SoC through a first wire coupled to the first communication pin, a second wire coupled to the second communication pin, and a first plurality of voltage rails;
- and
- a second PMIC, wherein the second PMIC:
- is coupled to the first wire and the second wire and a second plurality of voltage rails,
- is coupled to the first PMIC through a unidirectional synchronization channel between the first PMIC and the second PMIC and a bidirectional fault channel between the first PMIC and the second PMIC, and
- receives a sync signal from the first PMIC via the unidirectional synchronization channel in response to the first PMIC receiving a command from the SoC, the command causing a change in a power state of one or more voltage rails of the first plurality of voltage rails or the second plurality of voltage rails.
4 more elements
Dependencies are inferred from the claim text.