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US 12,182,051 B1Granted
Multi-purpose IO pads/bumps on semiconductor chips to maximize chip-to-chip data connectivity
AssigneeNuConcepts Holdings LLC
InventorBehzad Bahadori
Life of this patent
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AssigneeNuConcepts Holdings LLC
InventorBehzad Bahadori
Estimating the term…
Multi-purpose interface bumps on semiconductor chips may be used to optimize chip-to-chip data connectivity, including for example high speed chip-to-chip interfaces using fine-pitched bumps adaptable to interfaces with standard bumps without loss of total data rate. A chip with fine-pitch pads for μ-bumps may be connected to an organic package substrate with every other pad populated with a bump and connected to the organic package substrate, while adjacent pads are not populated with bumps and are deactivated. Total number of active bumps to 1/N for each data interface block, and the total bandwidth may be maintained by increasing the active bump data rate by N-times.
A data interface block on a first semiconductor chip comprising pads configurable to transfer a target data throughput either over N data lanes, where N is an integer greater than zero, with each of the N data lanes transferring 1/N of the target data throughput, wherein N fine-pitched bumps deposited on the pads are used to connect the N data lanes to a second semiconductor chip, or over a high-speed data lane transferring the target data throughput when a coarse-pitched bump on one of the pads is used to connect the high-speed data lane to the second semiconductor chip, wherein the data interface block further comprising N low-speed transmitter plus one high-speed transmitter and/or N low-speed receivers plus one high-speed receiver, wherein, when the data interface is connected to the second semiconductor chip over N data lanes using the N fine-pitch bumps, the N low-speed transmitters and/or N low-speed receivers are activated or connected to the fine-pitched bumps, with the high-speed transmitter and/or receiver deactivated or not connected to any bump.
A data interface block on a first semiconductor chip comprising pads configurable to transfer a target data throughput either over N data lanes, where N is an integer greater than zero, with each of the N data lanes transferring 1/N of the target data throughput, wherein N fine-pitched bumps deposited on the pads are used to connect the N data lanes to a second semiconductor chip, or over a high-speed data lane transferring the target data throughput when a coarse-pitched bump on one of the pads is used to connect the high-speed data lane to the second semiconductor chip, the data interface block further comprising N low-speed transmitters plus one high-speed transmitter and/or N low-speed receivers plus one high-speed receiver, wherein, when the data interface block is connected to the other semiconductor chip over the single high-speed data lane using a single coarse-pitch bump, the high-speed transmitter and/or the high-speed receiver are activated or connected to the coarse-pitched bump, with the N low-speed transmitters and/or receivers deactivated or not connected to any bump.
Dependencies are inferred from the claim text.