Chip-to-chip interface of a multi-chip module (MCM)

A multi-chip module (MCM), comprising:

• a first chip;
• a second chip;
• and
• a chip-to-chip interface that enables a transfer of data signals between the first chip and the second chip, comprising:
• bidirectional data links configured to transmit data signals and a direction indicator bit between the first chip and the second chip,
• wherein the direction indicator bit switches a direction of a data signal transmission in real-time;
• a clock link configured to transmit a clock signal common to the bidirectional data links between the first chip and the second chip,
• wherein the bidirectional data links and the clock link are comprised of conductive traces between the first and second chips and laid out to be of substantially equal length;
• a decoder configured to output a clock delay signal based upon a delay control signal;
• and
• a clock driver circuit having a digitally programmable clock signal delay that is based upon the clock delay signal, which prevents the clock signal from including multiple rising edges for a single transmission,
• wherein a timing of the clock signal is adjusted in response to the digitally programmable clock signal delay.