Data burst suspend mode using pause detection

A method comprising:

• monitoring, by a processing device operatively coupled to a plurality of pins, a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal;
• determining, by the processing device, whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition;
• in response to determining that the period of time satisfies the threshold condition, continuing, by the processing device, to monitor the logical level of the first pin;
• determining, by the processing device, whether the logical level of the first pin changed from the first logical level to a second logical level;
• and
• in response to determining that the logical level of the first pin changed from the first logical level to the second logical level, causing warmup cycles to be performed.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

• detecting that a first pin is at a first logical level while a data burst is active, wherein the first pin is comprised within a plurality of pins operatively coupled to the processing device, and wherein the first pin is associated with at least one of a read enable signal or a data strobe signal;
• in response to detecting that the first pin is at the first logical level, causing monitoring of a logical level of a first pin to be initiated;
• determining whether the data burst is being suspended based on a period of time in which the logical level of the first pin is held at the first logical level;
• in response to determining that the data burst is being suspended, continuing to monitor the logical level of the first pin;
• determining whether the logical level of the first pin changed from the first logical level to a second logical level;
• and
• in response to determining that the logical level of the first pin changed from the first logical level to the second logical level, causing warmup cycles to be performed.