Semiconductor device

A semiconductor device that executes neural network processing, comprising:

• n (n is an integer that is two or more) number of multiplier accumulators configured to multiply and accumulate pieces of input data and parameters;
• one or a plurality of memories configured to store the pieces of input data and the parameters;
• a first DMA (Direct Memory Access) controller configured to transfer the parameters stored in the memory to the n number of multiplier accumulators;
• a second input-side DMA controller configured to transfer the pieces of input data stored in the memory to the n number of multiplier accumulators, by use of n number of channels, respectively, and cause the n number of multiplier accumulators to perform calculations and to thereby output corresponding pieces of normal output data serving as the calculation results;
• a dummy circuit configured to output dummy data determined in advance to at least one or more of the n number of multiplier accumulators, thereby causing the at least one or more of the n number of multiplier accumulators to perform a dummy calculation and to output dummy output data serving as the dummy calculation result;
• a second output-side DMA controller configured to transfer the respective pieces of normal output data from the n number of multiplier accumulators to the memory, by use of n number of channels, and not to transfer the dummy output data from the at least one or more of the n number of multiplier accumulators to the memory;
• and
• a sequence controller configured to output a read start signal for starting the data transfer from the memory to the second input-side DMA controller,
• wherein the sequence controller divides the n number of channels of each of the second input-side DMA controller and the second output-side DMA controller and the n number of multiplier accumulators into m (m is an integer smaller than n) number of groups, and outputs, to the second input-side DMA controller, the read start signal for each of the m number of groups at different timings from one another, thereby controlling such that a series of operation timings including a read operation by the second input-side DMA controller, a calculation operation by the multiplier accumulator, and a write operation by the second output-side DMA controller is different from one another among the m number of groups.

A semiconductor device including one semiconductor chip, comprising:

• a neural network engine configured to execute neural network processing;
• one or a plurality of memories configured to store pieces of input data and parameters;
• a processor;
• and
• a bus configured to connect the neural network engine, the memories, and the processor with each other,
• wherein the neural network engine includes:
• n (n is an integer that is two or more) number of multiplier accumulators configured to multiply and accumulate pieces of input data and parameters;
• one or a plurality of memories configured to store the pieces of input data and the parameters;
• a first DMA (Direct Memory Access) controller configured to transfer the parameters stored in the memory to the n number of multiplier accumulators;
• a second input-side DMA controller configured to transfer the pieces of input data stored in the memory to the n number of multiplier accumulators, by use of n number of channels, respectively, and cause the n number of multiplier accumulators to perform calculations and to thereby output corresponding pieces of normal output data serving as the calculation results;
• a dummy circuit configured to output dummy data determined in advance to at least one or more of the n number of multiplier accumulators, thereby causing the at least one or more of the n number of multiplier accumulators to perform a dummy calculation and to output dummy output data serving as the dummy calculation result;
• and
• a second output-side DMA controller configured to transfer the respective pieces of normal output data from the n number of multiplier accumulators to the memory, by use of n number of channels, and not to transfer the dummy output data from the at least one or more of the n number of multiplier accumulators to the memory,
• wherein the at least one or more of the n number of multiplier accumulators perform the dummy calculation in a period from a timing at which the second output-side DMA controller ends data transfer to the memory to a timing at which the second input-side DMA controller starts data transfer from the memory.