Multi-chip module (MCM) with scalable high bandwidth memory

An integrated circuit (IC) processor chiplet, comprising:

• a high bandwidth memory (HBM) data interface that is configurable to operate in one of a first HBM mode of operation or a second HBM mode of operation;
• wherein during the first HBM mode of operation, the HBM data interface is configured to couple to multiple links forming N channels and to operate at an aggregate data rate R, the multiple links to couple the IC processor chiplet to at least two DRAM stacks on an active base die, each of the at least two DRAM stacks configured to couple to N/2 channels;
• and
• wherein during the second HBM mode of operation, the HBM data interface is configured to couple to the multiple links forming the N channels and to operate at the aggregate data rate R, the multiple links to couple the IC processor chiplet to one of the at least two HBM stacks at a time, each of the at least two HBM stacks configured to couple to the N channels.

A scalable high-bandwidth memory (HBM), comprising:

• a first HBM device coupled to an active base die that comprises active circuitry and comprising a first primary data interface to couple to an integrated circuit (IC) processor chiplet, the first primary data interface to couple to a first set of at least N/2 data channels and to operate at a first data transfer rate, the first HBM device comprising a first stack of memory die;
• a second HBM device coupled to the active base die and supporting a second set of at least N/2 data channels and to operate at a second data transfer rate, the second HBM device comprising a second stack of memory die that is separate from the first stack of memory die;
• and
• wherein the first HBM device and the second HBM device are configured to collectively couple to N channels and to operate at an aggregate data rate that is at most a sum of the first data transfer rate and the second data transfer rate.