Cache control to preserve register data

A method, comprising:

• decoding, by a computing system, instructions for execution, wherein the instructions indicate operations on register operand data;
• providing, by the computing system, memory backing for register operand data in one or more caches;
• controlling, by the computing system, a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated as being utilized by decoded instructions of the first thread;
• preserving, by the computing system, register operand data in the one or more caches, including preventing eviction of a given cache line from a cache based on an asserted lock indicator, wherein the asserted lock indicator is for a register for which operand data is stored in the given cache line;
• and
• clearing, by the computing system, the first set of lock indicators in response to a reset event.

A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:

• processor pipeline circuitry configured to perform operations on register operand data, wherein the processor pipeline circuitry includes decode circuitry configured to decode instructions for execution;
• memory hierarchy circuitry configured to provide memory backing for register operand data in one or more cache circuits;
• and
• lock circuitry configured to:
• control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by the decode circuitry, as being utilized by decoded instructions of the first thread;
• preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator, wherein the asserted lock indicator is for a register for which operand data is stored in the given cache line;
• and
• clear the first set of lock indicators in response to a reset event.