Latency reduction using stream cache
AssigneeMicron Technology, Inc.
InventorsMuthazhagan Balasubramani, Venkatesh Anandpadmanabhan
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AssigneeMicron Technology, Inc.
InventorsMuthazhagan Balasubramani, Venkatesh Anandpadmanabhan
Estimating the term…
A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.
A system comprising:
A method comprising:
A non-transitory computer readable medium including instructions, which when performed by a computer system comprising a memory device, and a processing device operatively coupled to the memory device, cause the computer system to perform operations comprising:
Dependencies are inferred from the claim text.