Opportunistic late depth testing to prevent stalling for overlapping cache lines

A semiconductor apparatus comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, the logic implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic to:
• determine whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing;
• and
• when the first cache line overlaps the second cache line:
• switch the first cache line to be allocated for late depth testing;
• and
• bypass an early depth test for the first cache line.

At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a graphics apparatus, cause the graphics apparatus to:

• determine whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing;
• and
• when the first cache line overlaps the second cache line:
• switch the first cache line to be allocated for late depth testing;
• and
• bypass an early depth test for the first cache line.

A method comprising:

• determining whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing;
• and
• when the first cache line overlaps the second cache line:
• switching the first cache line to be allocated for late depth testing;
• and
• bypassing an early depth test for the first cache line.