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US 12,182,021 B2Granted
Methods and apparatus to enable secure multi-coherent and pooled memory in an edge network
AssigneeIntel Corporation
InventorFrancesc Guim Bernat
Life of this patent
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Abstract
Methods, apparatus, systems and articles of manufacture are disclosed to enable secure memory sharing in a multi-tenant edge network. Examples disclosed herein include mapping a first node to a memory region in response to receiving a memory access request from a second node mapped to the memory region, providing a private security key associated with the memory region to the first node, and applying a cache coherency protocol to the first node and the second node in response to the pooled memory controller mapping the first node to the memory region.
Claims26
A server comprising:
- interface circuitry at a data center, the interface circuitry to communicate with an edge node and a base station in an edge network;
- memory including a memory region;
- machine-readable instructions;
- and
- at least one processor circuit to be programmed by the machine-readable instructions to:
- determine the base station is authorized to access the memory region of the memory;
- generate a private security key, the private security key to encrypt data corresponding to the memory region of the memory;
- map the edge node to the memory region after receiving a memory access request from the base station, the base station mapped to the memory region;
- provide the private security key associated with the memory region to the edge node;
- and
- apply a cache coherency protocol to the edge node and the base station in the edge network after the edge node is mapped to the memory region and after detection of an access of the memory region, the cache coherency protocol to maintain coherency of memory contents between the edge node and the base station.
8 more elements
A non-transitory computer readable medium comprising computer readable instructions to cause at least one processor circuit at a server to at least:
- determine a base station in an edge network is authorized to access a memory region in memory of the server;
- generate a private security key, the private security key to encrypt data corresponding to the memory region of the memory;
- map an edge node in the edge network to the memory region after a memory access request from the base station, the base station mapped to the memory region;
- provide the private security key associated with the memory region to the edge node;
- and
- apply a cache coherency protocol to the edge node and the base station in the edge network after the edge node is mapped to the memory region and after detection of an access of the memory region, the cache coherency protocol to maintain coherency of memory contents between the edge node and the base station.
3 more elements
An apparatus, comprising:
- security means for:
- determining a base station in an edge network is authorized to access a memory region of memory;
- and
- generating a private security key, the private security key to encrypt data corresponding to the memory region of the memory;
- means for mapping an edge node in the edge network to the memory region after a memory access request from the base station, the base station mapped to the memory region;
- means for providing the private security key associated with the memory region to the edge node;
- and
- means for applying a cache coherency protocol to the edge node and the base station in the edge network after the mapping of the edge node to the memory region and after detection of an access of the memory region, the cache coherency protocol to maintain coherency of memory contents between the edge node and the base station.
5 more elements
A method, comprising:
- determining, by at least one processor circuit programmed by at least one instruction, a base station in an edge network is authorized to access a memory region of memory of a server;
- generating a private security key, the private security key to encrypt data corresponding to the memory region of the memory;
- mapping, by one or more of the at least one processor circuit, an edge node in the edge network to the memory region after a memory access request from the base station, the base station mapped to the memory region;
- providing the private security key associated with the memory region to the edge node;
- and
- applying a cache coherency protocol to the edge node and the base station in the edge network after the mapping of the edge node to the memory region and after detection of an access of the memory region, the cache coherency protocol to maintain coherency of memory contents between the edge node and the base station.
3 more elements
Dependencies are inferred from the claim text.