Microprocessor that prevents same address load-load ordering violations using physical address proxies

A method, comprising:

• in a microprocessor comprising:
• a first-level cache and a second-level set associative cache that is inclusive of the first-level cache, wherein each entry of the second-level cache is uniquely identified by a set index and a way;
• a load queue, wherein each entry of the load queue is configured to hold:
• a load physical address proxy (PAP) for a load physical memory line address associated with a load instruction rather than holding the load physical memory line address itself, wherein the load PAP comprises the set index and the way that uniquely identifies the entry of the second-level cache that holds a copy of a line of memory specified by the load physical memory line address;
• and
• an indication of whether the load instruction has completed execution;
• performing a removal of a copy of a line of memory at a removal physical memory line address from an entry of the second-level cache;
• forming a removal PAP as a proxy for the removal physical memory line address, wherein the removal PAP comprises a set index and a way that uniquely identifies the removed entry;
• performing a snoop of the load queue with the removal PAP;
• and
• determining, based on the snoop, whether a condition is true, wherein the condition comprises:
• the removal PAP matches one or more load PAPs in one or more entries of the load queue associated with one or more load instructions that have completed execution;
• and
• if the condition is true, signaling an abort request.

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising:

• a first-level cache and a second-level set associative cache that is inclusive of the first-level cache, wherein each entry of the second-level cache is uniquely identified by a set index and a way;
• a load queue, wherein each entry of the load queue is configured to hold:
• a load physical address proxy (PAP) for a load physical memory line address associated with a load instruction rather than holding the load physical memory line address itself, wherein the load PAP comprises the set index and the way that uniquely identifies the entry of the second-level cache that holds a copy of a line of memory specified by the load physical memory line address;
• and
• an indication of whether the load instruction has completed execution;
• wherein the microprocessor is configured to:
• perform a removal of a copy of a line of memory at a removal physical memory line address from an entry of the second-level cache;
• form a removal PAP as a proxy for the removal physical memory line address, wherein the removal PAP comprises a set index and a way that uniquely identifies the removed entry;
• perform a snoop of the load queue with the removal PAP;
• and
• determine, based on the snoop, whether a condition is true, wherein the condition comprises:
• the removal PAP matches one or more load PAPs in one or more entries of the load queue associated with one or more load instructions that have completed execution;
• and
• if the condition is true, signal an abort request.