Instruction and micro-architecture support for decompression on core

One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:

• decode a decompression instruction into a first micro operation and a second micro operation, wherein the first micro operation is to cause one or more load operations to fetch data into one or more cachelines of a cache of a processor core;
• and
• cause Decompression Engine (DE) circuitry to decompress the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation, wherein the DE circuitry is to signal the processor core on completion of decompression of every cacheline.

A method comprising:

• decoding a decompression instruction into a first micro operation and a second micro operation, wherein the first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core;
• and
• causing Decompression Engine (DE) circuitry to decompress the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation, wherein the DE circuitry signals the processor core on completion of decompression of every cacheline.