Memory circuit with power registers

A method, comprising:

• receiving, by a memory circuit during a first processing cycle, a read command and an address, wherein the memory circuit includes a first storage circuit configured to store a plurality of data words, and a second storage circuit configured to store a subset of the plurality of data words, wherein the second storage circuit includes a plurality of register circuits configured to store corresponding ones of the subset of the plurality of data words and associated addresses, and wherein a first power consumption associated with retrieving a previously stored data word from the first storage circuit is greater than a second power consumption associated with retrieving the previously stored data from the second storage circuit;
• comparing the address to a plurality of addresses associated with the subset of the plurality of data words stored in corresponding ones of the plurality of register circuits;
• in response to determining that the address matches a particular address of the plurality of addresses, selecting a particular register circuit of the plurality of register circuits that stores the particular address;
• and
• in response to determining that the address included in the read command corresponds to a given data word included in the subset of the plurality of data words:
• de-activating the first storage circuit in a second processing cycle subsequent to the first processing cycle;
• retrieving, during the second cycle, the given data word from the second storage circuit;
• and
• generating an output signal using the given data word retrieved from the particular register circuit of the plurality of register circuits of the second storage circuit using a plurality of selection signals,
• wherein de-activating the first storage circuit in the second processing cycle includes activating at least one selection signal of the plurality of selection signals configured to retrieve desired data from the particular register circuit of the plurality of register circuits while deactivating the first storage circuit.

An apparatus, comprising:

• a processor circuit;
• and
• a cache memory circuit that includes a first storage circuit configured to store a plurality of data words, and a second storage circuit configured to store a subset of the plurality of data words, wherein a first power consumption associated with retrieving a previously stored data word from the first storage circuit is greater than a second power consumption associated with retrieving the previously stored data from the second storage circuit, wherein the second storage circuit includes a plurality of register circuits configured to store corresponding ones of the subset of the plurality of data words and associated addresses, and wherein the cache memory circuit is configured to:
• receive, from the processor circuit during a first processing cycle, a first read command and a first address;
• compare the first address to a plurality of addresses associated with the subset of the plurality of data words stored in corresponding ones of the plurality of register circuits;
• in response to a determination that the first address matches a particular address of the plurality of addresses, select a particular register circuit of the plurality of register circuits that stores the particular address;
• and
• in response to a determination that the first address corresponds to a given data word included in the subset of the plurality of data words:
• de-activate the first storage circuit in a second processing cycle subsequent to the first processing cycle;
• retrieve, during the second processing cycle, the given data word from the second storage circuit;
• and
• generate an output signal using the given data word retrieved from the particular register circuit of the plurality of register circuits of the second storage circuit using a plurality of selection signals,
• wherein to de-activate the first storage circuit in the second processing cycle, the cache memory circuit is further configured to activate at least one selection signal of the plurality of selection signals configured to retrieve desired data from the particular register circuit of the plurality of register circuits while deactivating the first storage circuit.