Fail-safe boot block to dynamically boot platform resiliency firmware

An information handling system, comprising:

• a central processing unit (CPU);
• an embedded controller (EC);
• and
• a computer readable memory, accessible to the processor, including processor executable instructions that, when executed by the CPU, cause the system to perform operations including:
• monitoring power on self-test (POST) messages of an information handling system;
• responsive to detecting a POST error message indicative of a POST error condition, executing a recovery sequence comprising a sequence of main basic input/output system (BIOS) recovery operations;
• responsive to determining the recovery sequence did not resolve the POST error condition, setting a resiliency boot block bit;
• executing a reset to boot the information handling system to a safe BIOS mode to determine a failure stage of the main BIOS;
• and
• taking corrective action based on the failure stage.

A non-transitory computer readable medium including processor executable instructions that, when executed by a processor of an information handling system, cause the information handling system to perform operations including:

• monitoring power on self-test (POST) messages of the information handling system;
• responsive to detecting a POST error message indicative of a POST error condition, executing a recovery sequence comprising a sequence of main basic input/output system (BIOS) recovery operations;
• responsive to determining the recovery sequence did not resolve the POST error condition, setting a resiliency boot block bit;
• executing a reset to boot the information handling system to a safe BIOS mode to determine a failure stage of the main BIOS;
• and
• taking corrective action based on the failure stage.