Small spacecraft processing and bus architecture

A spacecraft computing system, comprising:

• a first processor configured to process data from at least one payload and a first plurality of spacecraft systems;
• a second processor configured to process data from a second plurality of spacecraft systems;
• and
• an interface connected to the second processor configured to interface with a third spacecraft system,
• wherein the second processor is configured to monitor the first processor and to initiate a recovery of the first processor when the first processor experiences a fault,
• wherein the first processor's processing capacity is greater the second processor's processing capacity,
• wherein the first processor is configured to receive a first plurality of data signals from the at least one payload and the first plurality of spacecraft systems,
• wherein the first plurality of spacecraft systems comprises at least two of a camera head, a star tracker, a navigation front end, and radio receiver,
• wherein the first plurality of spacecraft systems do not include an embedded processor for each of the first plurality of spacecraft systems,
• wherein the second processor is configured to receive a second plurality of data signals from the second plurality of spacecraft systems,
• wherein the second plurality of spacecraft systems comprises at least two of a transceiver, propulsion system, sun sensor, inertial measurement unit, and magnetometer,
• wherein the first processor implements each of an autonomous maneuver planning and execution function, star tracking, global position system function, and digital radio function based on the received first plurality of data signals processed by the first processor, and
• wherein the second processor implements each of orbit control, attitude control system, housekeeping, command decoding, and data packetization based on the received second plurality of data signals processed by the second processor.