System and method of reducing logic for multi-bit error correcting codes

A method of generating an error correction circuit for correcting an error in a codeword read from a memory, comprising:

• constructing a generation matrix (G matrix) comprising a parity matrix (P matrix) and arranged in a systematic form;
• sorting rows of the P matrix into groups of different row weights in an ascending order of the row weights;
• determining a number of rows in the P matrix to be truncated;
• determining that a row number of first x groups of the sorted rows is less than a number of data bits k by a number q;
• forming a truncated P matrix from rows of the first x groups and q rows of the (x+1) group;
• and
• forming an error correction circuit in at least one of a digital electronic circuit, an application-specific integrated circuit, a field programmable gate array, and a computer circuit implemented as at least one of hardware, firmware and software according to the truncated P matrix.

A method of generating an error correction circuit for correcting an error in a codeword read from a memory, comprising:

• constructing a generation matrix (G matrix) having a t-bit error-correcting strength, the G matrix comprising a parity matrix (P matrix) and arranged in a systematic form;
• generating a syndrome for a retrieved data bit vector by using a check matrix (H matrix) based on the P matrix;
• combining u rows of the P matrix, u being a natural number not greater than t so as to truncate the P matrix;
• determining the error when the combined u rows match the syndrome;
• and
• generating an error correction circuit comprising a truncated P matrix through truncating rows of the P matrix for correcting the error of the codeword according to the syndrome, wherein a number of logic 1's in the truncated P matrix is minimized in response to truncating the P matrix,
• wherein the error correction circuit is generated in at least one of a digital electronic circuit, an application-specific integrated circuit, a field programmable gate array, and a computer circuit implemented as at least one of hardware, firmware and software.