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US 12,181,966 B2Granted
Reduction of latency impact of on-die error checking and correction (ECC)
AssigneeIntel Corporation
InventorsKuljit S. Bains, Narasimha Lanka
Life of this patent
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Abstract
A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.
Claims18
A memory device comprising:
- a memory array;
- a hardware interface to couple to a memory controller;
- and
- error checking and correction (ECC) circuitry to receive read data from an address of the memory array in response to a read command from the memory controller, perform error checking on the read data, detect a severity of error in the read data, encode an indication of errors to indicate the severity of error including a selection among no errors, corrected error, and uncorrected error, return the indication of errors, return the read data without application of error correction, apply error correction to the read data, and store corrected read data internally to the memory device.
1 more element
A memory controller comprising:
- a hardware interface to couple to a memory device;
- and
- command logic to generate a read command to an address of the memory device;
- wherein in response to the read command, the hardware interface is to receive data from the address without application of on-die error correction by error checking and correction (ECC) circuitry of the memory device and an encoded indication of errors to indicate a severity of error in the data including a selection among no errors, corrected error, and uncorrected error;
- and
- wherein in response to the indication of errors indicating a correctable, uncorrected error in the data, the command logic is to generate a subsequent read command to receive the data from the address with application of on-die error correction by the ECC circuitry of the memory device.
3 more elements
A system comprising:
- a memory device including:
- a memory array;
- and
- error checking and correction (ECC) circuitry to receive read data from an address of the memory array, perform error checking on the read data, detect a severity of error in the read data, encode an indication of errors to indicate the severity of error including a selection among no errors, corrected error, and uncorrected error, return the indication of errors, return the read data without application of error correction, apply error correction to the read data, and store corrected read data internally to the memory device;
- and
- a memory controller including:
- command logic to generate a read command to the address of the memory device;
- wherein in response to the read command, the memory device is to return the read data without application of error correction and the indication of errors.
5 more elements
Dependencies are inferred from the claim text.