Method and apparatus for fault prediction and management
AssigneeAdvanced Micro Devices, Inc.
InventorsSudhanva Gurumurthi, Vilas K. Sridharan
Life of this patent
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Abstract
A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.
Claims21
A method for predicting and managing a fault in memory, comprising:
- detecting an error in data that is read from the memory, wherein the detecting an error in data includes detecting a physical address for the error in the data;
- comparing the physical address to one or more stored errors using a filter, the comparing comprising applying a plurality of hash functions to the physical address to obtain a set of bit positions;
- classifying the error as a permanent error based on whether a set of bit values at each bit position is equal to 1;
- and
- updating a machine check architecture (MCA) to indicate that the physical address contains the permanent error in response to the error being classified as the permanent error, wherein the MCA includes a vector identifying a bit error of bits stored at the physical address.
An apparatus for predicting and managing a fault in a memory, comprising:
- a filter;
- a machine check architecture (MCA);
- and
- a memory controller that is communicatively coupled with the memory, the filter and the MCA,
- wherein the memory controller:
- detects an error in data that is read from the memory, wherein the detecting an error in data includes detecting a physical address for the error in the data,
- compares the physical address to one or more stored errors using the filter, the comparing comprising applying a plurality of hash functions to the physical address to obtain a set of bit positions,
- classifies the error as a permanent error based on whether a set of bit values at each bit position is equal to 1, and
- update the MCA to indicate that the physical address contains the permanent error in response to the error being classified as the permanent error, wherein the MCA includes a vector identifying a bit error of bits stored at the physical address.
A non-transitory computer-readable medium for predicting and managing a fault in memory, the non-transitory computer-readable medium having instructions recorded thereon, that when executed by a processor, cause the processor to perform operations including:
- detecting an error in data that is read from the memory, wherein the detecting an error in data includes detecting a physical address for the error in the data;
- comparing the physical address to one or more stored errors using a filter, the comparing comprising applying a plurality of hash functions to the physical address to obtain a set of bit positions;
- classifying the error as a permanent error based on whether a set of bit values at each bit position is equal to 1;
- and
- updating a machine check architecture (MCA) to indicate that the physical address contains the permanent error in response to the error being classified as the permanent error, wherein the MCA includes a vector identifying a bit error of bits stored at the physical address.
Dependencies are inferred from the claim text.