US 12,181,958 B2 · Scalable architecture for error capturing with single logger approach for automotive systems

Abstract

Various embodiments include methods and devices for error capturing implemented in a computing device. Embodiments may include receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger, including an error data for a memory of a processor having an identification of at least one faulty bit of the memory. Embodiments may include receiving a plurality of requests from a plurality of error capture modules for the processor at an error selection module for the processor, and retrieving an error data from an error capture module by the error selection module in response to a request from the error capture module being ordered prior to another request from another error capture module. Embodiments may include sending the error data to the error logger, and storing the error data at the error logger in an order relative to another error data.

Claims30

Dependent claims

A method of error capturing implemented in a computing device, comprising:

receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.

A computing device, comprising:

a plurality of memories;
a plurality of processors coupled to the plurality of memories;
and
an error logger coupled to the plurality of memories and configured to receive a plurality of error data for the plurality of memories of the plurality of processors at the error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.

2 more elements

A computing device, comprising:

a plurality of memories;
a plurality of processors coupled to the plurality of memories;
an error logger coupled to the plurality of memories;
and
means for receiving a plurality of error data for the plurality of memories of the plurality of processors at the error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.

3 more elements

Dependencies are inferred from the claim text.

Scalable architecture for error capturing with single logger approach for automotive systems

Life of this patent

Scalable architecture for error capturing with single logger approach for automotive systems

Life of this patent

Abstract

Claims30