Boot time for autonomous drones

A method comprising:

• loading an operating system to control the autonomous drone from a first memory to a second memory, wherein the second memory is a higher-power memory that consumes more power than the first memory;
• entering an on state;
• in response to a first timeout or a command to turn off the autonomous drone, enter a standby state from the on state, wherein the standby state has a first power state and the on state has a second power state;
• in response to a second timeout or a first condition, entering an off state from the standby state, the off state having a third power state;
• and
• in response to a third timeout or a second condition, entering a power off state, the power off state having a fourth power state, wherein the first power state of the on state, the second power state of the standby state, and the third power state of the off state maintain power to the second memory, and wherein the fourth power state of the power off state does not provide power to the second memory.

A non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium including instructions that, when executed by a at least one processor, cause the at least one processor to perform operations comprising:

• loading an operating system to control the autonomous drone from a first memory to a second memory, wherein the second memory is a higher-power memory that consumes more power than the first memory;
• entering an on state;
• in response to a first timeout or a command to turn off the autonomous drone, enter a standby state from the on state, wherein the standby state has a first power state and the on state has a second power state;
• in response to a second timeout or a first condition, entering an off state from the standby state, the off state having a third power state;
• and
• in response to a third timeout or a second condition, entering a power off state, the power off state having a fourth power state, wherein the first power state of the on state, the second power state of the standby state, and the third power state of the off state maintain power to the second memory, and wherein the fourth power state of the power off state does not provide power to the second memory.