Automatic overclocking controller based on circuit delay measurement

An automatic overclocking controller based on a circuit delay measurement, comprising a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller, wherein

• a phase of a shadow clock (SCLK) output by the clock generator is adjusted from 0° to 360°, the TDM controller controls a circuit delay detector to sample the clock generator N times in a same phase before moving to a next phase, until the clock generator is sampled in all phases, and a final sampling value of each phase of the all phases is an average value of sampling values obtained from N times of sampling in a current phase;
• the TDM controller is further configured to perform a horizontal multi-frame fusion on final sampling values of the all phases to obtain transition points θ1 and θ2;
• when the horizontal multi-frame fusion is performed, the final sampling value of each phase is defined as one frame of data;
• therefore, an nth frame of data obtained after the horizontal multi-frame fusion is an average value of an
• (
• n
• -
• M
• -
• 1
• 2
• )
• t
• ⁢
• h
• frame of data to an
• (
• n
• +
• M
• -
• 1
• 2
• )
• t
• ⁢
• h
• frame of data, wherein M represents a coefficient of the horizontal multi-frame fusion;
• the transition point θ1 is a point wherein a sampling value changes from 0 to 1 after the horizontal multi-frame fusion, and the transition point θ2 is a point wherein a sampling value changes from 1 to 0 after the horizontal multi-frame fusion;
• and
• the CPU is configured to obtain the transition points θ1 and θ2 from the TDM controller to calculate a circuit delay td, and determine a frequency fnext of an accelerator for a next operating cycle based on the circuit delay td.