US 12,181,802 B2 · Semiconductor devices

Abstract

A semiconductor device includes a substrate including a cell region and a scribe lane surrounding the cell region, a first overlay pattern structure, which is on the scribe lane and includes first sub-patterns extending in a first direction parallel to an upper surface of the substrate, second sub-patterns extending in a second direction parallel to the upper surface of the substrate, a first outer fence surrounding the first sub-patterns and the second sub-patterns in a plan view and defining a first overlay pattern region, and a first inner fence in the first overlay pattern region and between the first sub-patterns and the second sub-patterns, and a lower structure in the cell region and on the scribe lane and between the first sub-patterns, the second sub-patterns, the first outer fence, and the first inner fence.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate comprising a cell region and a scribe lane surrounding the cell region;
a first overlay pattern structure on the scribe lane, wherein the first overlay pattern structure comprises:
a plurality of first sub-patterns extending in a first direction parallel to an upper surface of the substrate;
a plurality of second sub-patterns extending in a second direction parallel to the upper surface of the substrate;
a first outer fence surrounding the plurality of first sub-patterns and the plurality of second sub-patterns in a plan view and defining a first overlay pattern region;
and
a first inner fence in the first overlay pattern region and between the plurality of first sub-patterns and the plurality of second sub-patterns;
and
a lower structure in the cell region and on the scribe lane and between the plurality of first sub-patterns, the plurality of second sub-patterns, the first outer fence, and the first inner fence.

6 more elements

A semiconductor device comprising:

a substrate comprising a cell region and a scribe lane surrounding the cell region;
a lower structure in the cell region and on the scribe lane and comprising a first insulating layer and a second insulating layer on the first insulating layer;
a first overlay pattern structure on the scribe lane, wherein the first overlay pattern structure comprises:
a plurality of first overlay patterns extending in a first direction parallel to an upper surface of the substrate and spaced apart from each other in a second direction parallel to the upper surface of the substrate;
and
a first outer fence surrounding the plurality of first overlay patterns in a plan view, defining a first overlay pattern region, penetrating the first and second insulating layers, and extending in a third direction perpendicular to the upper surface of the substrate;
and
a second overlay pattern structure on the scribe lane, wherein the second overlay pattern structure comprises:
a plurality of second overlay patterns extending in the first direction parallel to the upper surface of the substrate and spaced apart from each other in the second direction;
and
a second outer fence surrounding the plurality of second overlay patterns in the plan view, defining a second overlay pattern region, penetrating the first and second insulating layers, and extending in the third direction.

8 more elements

A semiconductor device comprising:

a substrate comprising a cell region and a scribe lane surrounding the cell region;
a peripheral circuit transistor in the cell region;
a lower structure on the peripheral circuit transistor in the cell region and on the scribe lane and comprising a first insulating layer and a second insulating layer on the first insulating layer;
a memory cell array on the lower structure in the cell region;
a first overlay pattern structure on the scribe lane, wherein the first overlay pattern structure comprises:
a plurality of first overlay patterns extending in a first direction parallel to an upper surface of the substrate and spaced apart from each other in a second direction parallel to the upper surface of the substrate;
and
a first outer fence surrounding the plurality of first overlay patterns in a plan view, defining a first overlay pattern region, penetrating the first and second insulating layers, and extending in a third direction perpendicular to the upper surface of the substrate;
and
a second overlay pattern structure on the scribe lane, wherein the second overlay pattern structure comprises:
a plurality of second overlay patterns extending in the first direction parallel to the upper surface of the substrate and spaced apart from each other in the second direction;
and
a second outer fence surrounding the plurality of second overlay patterns in the plan view, defining a second overlay pattern region, penetrating the first and second insulating layers, and extending in the third direction.

10 more elements

Dependencies are inferred from the claim text.

Semiconductor devices

Life of this patent

Semiconductor devices

Life of this patent

Abstract

Claims20