Display panel, array substrate, and manufacturing method thereof

A method of manufacturing an array substrate, comprising:

• providing a substrate, forming a first electrode layer on the substrate, the first electrode layer comprising a first common electrode;
• forming a first insulating layer on the first electrode layer;
• forming a semiconductor layer on the first insulating layer;
• forming a second electrode layer on the semiconductor layer, wherein the second electrode layer covers the first insulating layer, the second electrode layer comprises a drain electrode, a source electrode, and a second common electrode, and the drain electrode and the source electrode are respectively connected to the semiconductor layer;
• forming a first passivation layer on the second electrode layer;
• and
• forming a third electrode layer on the first passivation layer, the third electrode layer comprising a pixel electrode and a first connection electrode;
• wherein an orthographic projection of the first common electrode on the substrate at least partially overlaps with an orthographic projection of the pixel electrode on the substrate, and the first connection electrode is connected to the second common electrode and the first common electrode through an opening penetrating the first insulating layer and the first passivation layer.

A display panel, comprising an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate;

• wherein the array substrate comprises:
• a substrate;
• a first electrode layer disposed on the substrate, and the first electrode layer comprising a first common electrode;
• a first insulating layer disposed on the first electrode layer;
• a semiconductor layer disposed on the first insulating layer;
• a second electrode layer disposed on the semiconductor layer and covering the first insulating layer, wherein the second electrode layer comprises a drain electrode, a source electrode, and a second common electrode, and the drain electrode and the source electrode are respectively connected to the semiconductor layer;
• a first passivation layer disposed on the second electrode layer;
• and
• a third electrode layer disposed on the first passivation layer, and the third electrode layer comprising a pixel electrode;
• wherein an orthographic projection of the first common electrode on the substrate at least partially overlaps with an orthographic projection of the pixel electrode on the substrate, and the second common electrode is connected to the first common electrode through an opening in the first insulating layer;
• and
• wherein the third electrode layer further comprises a first connection electrode, and the first connection electrode is connected to the second common electrode and the first common electrode through an opening penetrating the first insulating layer and the first passivation layer.