Integrated circuit having test circuitry for memory sub-systems

A system, comprising:

• test control circuitry configured to perform scan testing of a plurality of scan chains;
• a first compiled memory of a first size generated by a memory compiler, the first compiled memory comprising:
• a first memory array;
• a first pre-decode circuit;
• and
• a first plurality of latches, each configured to operate as part of the plurality of scan chains, wherein each latch of the first plurality of latches has, in addition to a scan input, a data input coupled to a corresponding pin of the first memory and an output coupled to the first pre-decode circuit;
• and
• a second compiled memory of a second size, smaller than the first size, generated by the memory compiler, the second compiled memory comprising:
• a second memory array;
• a second pre-decode circuit;
• and
• a second plurality of address latches, each configured to operate as part of the plurality of scan chains, wherein:
• a first set of the second plurality of latches each has a data input coupled to a corresponding pin of the second compiled memory, each has a scan input, and each has an output coupled to the second pre-decode circuit, and
• a second set of the second plurality of latches each has a data input coupled to a data input of at least one latch in the first set of the second plurality of latches, each has a scan input, and each is configured to provide no input to the second pre-decode circuit, wherein no latch of the first set is in the second set and no latch of the second set is in the first set.

A system, comprising:

• a plurality of compiled memories, each compiled memory including N corresponding latches coupled between a corresponding set of X address pins and a corresponding pre-decoder, the corresponding pre-decoder configured to provide pre-decoded address bits which address a selected storage location in a corresponding memory array, wherein each of N and X is an integer greater than or equal to one, and wherein:
• in each compiled memory, the set of N corresponding latches includes a set of X used latches and a set of Y unused latches such that N=X+Y, Y being an integer greater than or equal to one, wherein:
• each of the one or more X used latches has a data input coupled to a corresponding address pin of the corresponding set of X address pins with a one-to-one correspondence between the X latches and the X address pins, a scan input, and an output configured to provide an input to the corresponding pre-decoder, and
• each of the one or more Y unused latches is configured to not provide any input to the corresponding pre-decoder, and has a data input coupled to a data input of a used latch within the set of X used latches of the compiled memory and to the corresponding address pin of the used latch, and has a scan input.