Multi-input multi-output first-in first-out buffer circuit that reads out multiple data flits at once, and electronic circuits having same
AssigneeSamsung Electronics Co., Ltd.
InventorYewon Lee
Life of this patent
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Abstract
Disclosed is a MIMO FIFO buffer circuit that reads out data flits at once as many as an internal pointer increment value. The MIMO FIFO buffer circuit includes a MIMO FIFO storage array including ‘Y’ storage blocks, and an internal pointer generator that generates an internal pointer based on an internal pointer increment value indicating the number of data flits to read out at once from among ‘K×X’ data flits stored in K storage blocks out of the ‘Y’ storage blocks. Each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’, and each of the ‘K’ storage blocks stores ‘X’ data flits.
Claims20
A multi-input multi-output first-in-first-out (MIMO FIFO) buffer circuit comprising:
- a MIMO FIFO storage array including ‘Y’ storage blocks;
- and
- an internal pointer generator configured to generate an internal pointer based on an internal pointer increment value indicating the number of data flits to read out at once from among ‘K×X’ data flits stored in K storage blocks out of the ‘Y’ storage blocks,
- wherein each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’, and
- wherein each of the ‘K’ storage blocks is configured to store ‘X’ data flits.
A data processing circuit comprising:
- a storage array including ‘Y’ storage blocks;
- a write control logic circuit configured to receive ‘X’ data flits output from each of ‘K’ data packet generation circuits and to write the ‘X’ data flits to each of ‘K’ storage blocks among the ‘Y’ storage blocks;
- and
- a readout circuit configured to read out a number of data flits at once corresponding to an internal pointer increment value starting from a first data flit specified by an output pointer and an internal pointer from among ‘K×X’ data flits stored in the ‘K’ storage blocks,
- wherein each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’.
A data processing system comprising:
- ‘K’ data packet generation circuits, each of which is configured to generate a data packet including ‘X’ data flits;
- and
- a data processing circuit connected to the ‘K’ data packet generation circuits,
- wherein the data processing circuit includes an MIMO FIFO buffer circuit,
- wherein the MIMO FIFO buffer circuit includes:
- a storage array including ‘Y’ storage blocks;
- a write control logic circuit configured to receive ‘X’ data flits output from the each of ‘K’ data packet generation circuits and to write the ‘X’ data flits to each of ‘K’ storage blocks among the ‘Y’ storage blocks;
- and
- a readout circuit configured to read out a number of data flits at once corresponding to an internal pointer increment value starting from a first data flit specified by an output pointer and an internal pointer, from among ‘K×X’ data flits stored in the ‘K’ storage blocks, and
- wherein each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’.
Dependencies are inferred from the claim text.