Low power single phase logic gate latch for clock-gating

A method comprising:

• receiving an enable signal by an input port of a latch;
• receiving, by a latch, an input data signal on gates of a first P-type transistor and a first N-type transistor of a first transistor stack, wherein a value of the input data signal is based at least in part on a value of the enable signal;
• receiving an inverted version of the input data signal on gates of a second P-type transistor and a second N-type transistor of a second transistor stack, wherein the first transistor stack is cross-coupled to the second transistor stack;
• receiving an input clock signal at a P-type clocked transistor coupled between the first transistor stack and the second transistor stack;
• receiving the input clock signal at an N-type clocked transistor connected to a common point of the cross-coupled first and second transistor stacks;
• and
• generating an output data signal by inverting an internal node of the cross-coupled first and second transistor stack.

An apparatus comprising:

• an input port configured to receive an enable signal;
• a data port configured to receive an input data signal, wherein a value of the input data signal is based at least in part on a value of the enable signal;
• a clock port configured to receive a clock signal;
• a first transistor stack connected between a supply voltage and ground;
• a second transistor stack connected between the supply voltage and ground;
• an N-type clocked transistor configured to receive the clock signal from the clock port, wherein the N-type clocked transistor is coupled to a common point of both the first transistor stack and the second transistor stack;
• and
• a P-type clocked transistor configured to receive the clock signal from the clock port, wherein the P-type clocked transistor is coupled between the first transistor stack and the second transistor stack;
• wherein the apparatus is configured to generate an output data signal from the input data signal based on a first inverter coupled to the first and second transistor stacks.