Flip flop and design method for integrated circuit including same

A flip-flop disposed in an integrated circuit (IC) layout, the IC circuit layout including alternating power lines defining rows of the IC circuit layout there between, the rows each extending lengthwise in a first direction, the flip-flop comprising:

• a first sub-master latch disposed in one of a first row and an adjacent second row among the rows of the IC circuit layout, and configured to generate a signal at a first node in response to a first data signal, a clock signal, and a signal at a second node;
• a second sub-master latch disposed in the other one of the first row and the second row in which the first sub-master latch is not disposed, wherein the second sub-master latch is configured to generate a signal at the second node in response to an inverted first data signal, the clock signal, and the signal at the first node;
• a first sub-slave latch disposed in one of the first row and the second row, and configured to generate a signal at a third node in response to the clock signal, the signal at the first node, and a signal at a fourth node;
• a second sub-slave latch disposed in the other one of the first row and the second row in which the first sub-slave latch is not disposed, wherein the second sub-slave latch is configured to generate the signal at the fourth node in response to the clock signal, the signal at the second node, and the signal at the third node,
• a third sub-master latch disposed in one of a third row adjacent to the second row and a fourth row adjacent to the third row, and configured to generate a signal at a fifth node in response to a second data signal, the clock signal, and a signal at a sixth node;
• a fourth sub-master latch disposed in the other one of the third row and the fourth row in which the third sub-master latch is not disposed, wherein the fourth sub-master latch is configured to generate the signal at the sixth node in response to an inverted second data signal, the clock signal, and the signal at the fifth node;
• a third sub-slave latch disposed in one of the third row and the fourth row, and configured to generate a signal at a seventh node in response to the clock signal, the signal at the fifth node, and a signal at an eighth node;
• and
• a fourth sub-slave latch disposed in the other one of the third row and the fourth row in which the third sub-slave latch is not disposed, wherein the fourth sub-slave latch is configured to generate the signal at the eighth node in response to the clock signal, the signal at the sixth node, and the signal at the seventh node,
• wherein the first sub-master latch and the second sub-master latch are adjacently disposed in a second direction in different ones of the first and second rows, the second direction perpendicular to the first direction,
• the first sub-slave latch and the second sub-slave latch are adjacently disposed in the second direction in different ones of the first and second rows,
• the third sub-master latch and the fourth sub-slave latch are adjacently disposed in the second direction in different ones of the third and fourth rows, and
• the fourth sub-master latch and the third sub-slave latch are adjacently disposed in the second direction in different ones of the third and fourth rows.

A flip-flop disposed in an integrated circuit (IC) layout, the IC circuit layout including alternating power lines defining rows of the IC circuit layout there between, the rows extending lengthwise in a first direction, the flip-flop comprising:

• a first sub-master latch disposed in one of a first row and an adjacent second row among the rows of the IC circuit layout, and configured to generate a signal at a first node in response to a first data signal, a clock signal, and a signal at a second node;
• a second sub-master latch disposed in the other one of the first row and the second row in which the first sub-master latch is not disposed, wherein the second sub-master latch is configured to generate a signal at the second node in response to an inverted first data signal, the clock signal, and the signal at the first node;
• a first sub-slave latch disposed in one of the first row and the second row, and configured to generate a signal at a third node in response to the clock signal, the signal at the first node, and a signal at a fourth node;
• a second sub-slave latch disposed in the other one of the first row and the second row in which the first sub-slave latch is not disposed, wherein the second sub-slave latch is configured to generate the signal at the fourth node in response to the clock signal, the signal at the second node, and the signal at the third node,
• a third sub-master latch disposed in one of a third row adjacent to the second row and a fourth row adjacent to the third row, and configured to generate a signal at a fifth node in response to a second data signal, the clock signal, and a signal at a sixth node;
• a fourth sub-master latch disposed in the other one of the third row and the fourth row in which the third sub-master latch is not disposed, wherein the fourth sub-master latch is configured to generate the signal at the sixth node in response to an inverted second data signal, the clock signal, and the signal at the fifth node;
• a third sub-slave latch disposed in one of the third row and the fourth row, and configured to generate a signal at a seventh node in response to the clock signal, the signal at the fifth node, and a signal at an eighth node;
• and
• a fourth sub-slave latch disposed in the other one of the third row and the fourth row in which the third sub-slave latch is not disposed, wherein the fourth sub-slave latch is configured to generate the signal at the eighth node in response to the clock signal, the signal at the sixth node, and the signal at the seventh node,
• wherein the first sub-master latch and the second sub-slave latch are adjacently disposed in a second direction in different ones of the first and second rows, the second direction perpendicular to the first direction,
• the first sub-slave latch and the second sub-master latch are adjacently disposed in the second direction in different ones of the first and second rows,
• the third sub-master latch and the fourth sub-slave latch are adjacently disposed in the second direction in different ones of the third and fourth rows, and
• the fourth sub-master latch and the third sub-slave latch are adjacently disposed in the second direction in different ones of the third and fourth rows.