Frequency divider and memory device including the same

A method of operating a frequency divider having a frequency dividing core circuit comprising a plurality of drive transistors and latch transistors, the method comprising:

• generating a body bias control signal based on clock frequency information;
• adjusting a DC level of a body bias based on the body bias control signal;
• and
• applying the body bias with the DC level that was adjusted to a body of one or more of the plurality of drive transistors and latch transistors.

A memory device comprising:

• a bank comprising at least one memory cell array;
• a bank controller configured to control the bank;
• a data buffer configured to transmit write data to the bank or to receive read data from the bank;
• a clock buffer configured to receive a clock;
• a data clock buffer configured to receive a data clock;
• a synchronization circuit configured to perform phase synchronization on the data clock based on the clock and to output a synchronized data clock;
• an internal clock generator comprising a frequency divider, and configured to generate at least one internal clock based on the synchronized data clock;
• a serializer configured to operate based on the at least one internal clock and to serialize bits of the read data;
• and
• a deserializer configured to operate based on the at least one internal clock and to deserialize bits of the write data, and
• wherein the frequency divider comprises:
• a frequency dividing core circuit comprising a first latch that comprises first and second drive transistors in a differential pair structure and first and second latch transistors in a cross-coupled structure, and a second latch comprising third and fourth drive transistors in the differential pair structure and third and fourth latch transistors with the cross-coupled structure, and configured to divide the synchronized data clock to generate first to fourth internal clocks;
• a controller configured to generate a body bias control signal based on clock frequency information indicating a frequency of the synchronized data clock;
• and
• an adaptive body bias (ABB) generator configured to adjust a respective DC level of each of the first and second body biases based on the body bias control signal, to apply the first body bias with the adjusted respective DC level to a respective body of each of the first, second, third, and fourth drive transistors, and to apply the second body bias with the adjusted respective DC level to a respective body of each of the first, second, third, and fourth latch transistors.