Flip-flop, master-slave flip-flop, and operating method thereof

A master-slave flip-flop comprising:

• a master latch including,
• an input switching circuit including at least one first transistor, the input switching circuit being configured to output an intermediate signal to a middle node based on a master input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal,
• a latch circuit including at least one second transistor, the latch circuit being connected to the middle node, and the latch circuit being configured to output a slave input signal based on the intermediate signal, and
• a blocking circuit configured to block application of a driving voltage to the at least one first transistor and the at least one second transistor in response to receiving a reset signal representing a logic level;
• and
• a slave latch configured to output an output signal synchronized with the at least one of the clock signal or the inverted clock signal based on the slave input signal provided from the master latch.