Phase-change memory including phase-change elements in series with respective heater elements and methods for manufacturing, programming, and reading thereof

A method of manufacturing a phase-change memory, the method comprising:

• forming, in a semiconductor body, a selection transistor;
• forming an electrical-insulation body on the semiconductor body;
• forming a conductive region through the electrical-insulation body, electrically coupled to the selection transistor;
• forming a plurality of heaters in the electrical-insulation body, each heater including a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region;
• forming a plurality of phase-change material features extending in the electrical-insulation body and including data-storage regions, each data-storage region being electrically and thermally coupled to one respective heater at the second end of the respective heater, wherein each of the plurality of phase-change material features is a continuous strip along a direction parallel to a major surface of the semiconductor body, and wherein a subset of the plurality of heaters is disposed at different locations along each of the continuous strip and separated by insulating regions;
• and
• forming a sealing layer of dielectric or insulating material covering sidewalls of a stack comprising one of the heaters and the respective one of the data storage regions coupled to it, the sealing layer capping a top major surface of the respective one of the data storage regions, wherein a portion of the electrical-insulation body covers the sealing layer above the stack.

A phase-change memory (PCM) comprising:

• a semiconductor body comprising a 2-D array of selection transistors;
• a 3-D memory array disposed over the semiconductor body;
• each of the 2-D array of selection transistors being coupled to a 1-D vertical array of the 3-D memory array to form a multilevel memory cell;
• a row of the multilevel memory cells along a first direction parallel to a major surface of the semiconductor body, the row of the multilevel memory cells comprising:
• stacked layers of electrically electrical-insulation bodies disposed over each other;
• stacked rows of conductive regions electrically coupled to one of the selection transistors from the respective row of the multilevel memory cell, each row of the conductive regions arranged along the first direction;
• stacked rows of heaters, each of the heaters including a first end in electrical contact with a respective conductive region and a second end that extends away from the conductive region, each row of the heaters arranged along the first direction;
• a stack of continuous strips of a phase change material, each of the continuous strips being disposed along the first direction, each of the continuous strips comprising data storage regions, each of the data storage regions being electrically and thermally coupled to one of the heaters at the second end of the respective heater, and wherein the heaters associated with the data storage regions are disposed at different locations along each of the continuous strip and separated by insulating regions;
• and
• a plurality of sealing layers of insulating material covering sidewalls of a stack comprising one of the heaters and the respective one of the data storage regions coupled to it, each of the sealing layers capping a top major surface of the respective one of the data storage regions, wherein a portion of one of the electrical-insulation bodies separates the stack with the respective sealing layer from one of the conductive regions above.