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US 12,120,926 B2Granted
Display panel, array substrate, and method of manufacturing thereof
AssigneeWuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
InventorSihang Bai
Life of this patent
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Abstract
A display panel, an array substrate, and a method of manufacturing thereof are provided, and the method includes: forming a semiconductor material layer, a barrier component, a first insulating layer, a gate, a second insulating layer, and an interlayer dielectric layer on the array substrate in order, performing a photolithographic process on the first insulating layer, gate, second insulating layer, and interlayer dielectric layer with a predetermined mask, forming a first via hole, a second via hole, and a groove; forming a source, drain, metal component and; and forming a planarization layer.
Claims15
A method of manufacturing an array substrate, wherein the array substrate comprises:
- a substrate;
- a semiconductor component, wherein the semiconductor component is formed on the substrate;
- a first insulating layer, wherein the first insulating layer covers the semiconductor component;
- a gate, wherein the gate is formed on the first insulating layer;
- a second insulating layer, wherein the second insulating layer covers the gate;
- an interlayer dielectric layer, wherein the interlayer dielectric layer covers the second insulating layer;
- a source, wherein at least a portion of the source is filled into a first via hole, and the source is electrically connected to the semiconductor component;
- a drain, wherein at least a portion of the drain is filled into a second via hole, and the drain is electrically connected to the semiconductor component;
- a barrier component, wherein the barrier component is formed on a same level layer as the semiconductor component, and the barrier component and the semiconductor component comprise a same material;
- a metal component, wherein at least a portion of the metal component is filled into a groove;
- and
- a planarization layer, wherein the planarization layer is disposed on the interlayer dielectric layer and covers the groove;
- and
- wherein the first via hole and the second via hole are formed in a display area of the array substrate, a bottom of the first via hole and a bottom of the second via hole are connected to the semiconductor component, the groove is formed in the bending area of the array substrate, and the barrier component is formed in the bending area, and
- wherein the groove comprises a first groove and a second groove, an opening of the second groove is formed at a bottom of the first groove, and the barrier component is formed at a bottom of the first groove and exposes the opening of the second groove,
- wherein the method comprises steps as follows:
- step A:
- forming the semiconductor component, the barrier component, the first insulating layer, the gate, the second insulating layer, and the interlayer dielectric layer on the array substrate in order;
- step B:
- performing a photolithographic process on the first insulating layer, the gate, the second insulating layer, and the interlayer dielectric layer with a predetermined mask;
- forming the first via hole, the second via hole, and the groove on the first insulating layer, the gate, the second insulating layer, and the interlayer dielectric layer by etching;
- step C:
- forming a metal layer in the first via hole, the second via hole, and the groove, wherein the source, the drain, and the metal component are formed by the metal layer;
- and
- step D:
- forming the planarization layer, wherein the planarization layer is disposed on the interlayer dielectric layer and covers the groove.
23 more elements
An array substrate, comprising:
- a substrate;
- a semiconductor component, wherein the semiconductor component is formed on the substrate;
- a first insulating layer, wherein the first insulating layer covers the semiconductor component;
- a gate, wherein the gate is formed on the first insulating layer;
- a second insulating layer, wherein the second insulating layer covers the gate;
- an interlayer dielectric layer, wherein the interlayer dielectric layer covers the second insulating layer;
- a source, wherein at least a portion of the source is filled into a first via hole, and the source is electrically connected to the semiconductor component;
- a drain, wherein at least a portion of the drain is filled into a second via hole, and the drain is electrically connected to the semiconductor component;
- a barrier component, wherein the barrier component is formed on a same level layer as the semiconductor component, and the barrier component and the semiconductor component comprise a same material;
- a metal component, wherein at least a portion of the metal component is filled into a groove;
- and
- a planarization layer, wherein the planarization layer is disposed on the interlayer dielectric layer and covers the groove;
- and
- wherein the first via hole and the second via hole are formed in a display area of the array substrate, a bottom of the first via hole and a bottom of the second via hole are connected to the semiconductor component, the groove is formed in the bending area of the array substrate, and the barrier component is formed in the bending area, and
- wherein the groove comprises a first groove and a second groove, an opening of the second groove is formed at a bottom of the first groove, and the barrier component is formed at a bottom of the first groove and exposes the opening of the second groove.
12 more elements
A display panel, comprising:
- an array substrate, a pixel definition layer, an anode, an organic light emitting layer, a cathode, and a packaging layer, wherein the array substrate comprises:
- a substrate;
- a semiconductor component, wherein the semiconductor component is formed on the substrate;
- a first insulating layer, wherein the first insulating layer covers the semiconductor component;
- a gate, wherein the gate is formed on the first insulating layer;
- a second insulating layer, wherein the second insulating layer covers the gate;
- an interlayer dielectric layer, wherein the interlayer dielectric layer covers the second insulating layer;
- a source, wherein at least a portion of the source is filled into a first via hole, and the source is electrically connected to the semiconductor component;
- a drain, wherein at least a portion of the drain is filled into a second via hole, and the drain is electrically connected to the semiconductor component;
- a barrier component, wherein the barrier component is formed on a same level layer as the semiconductor component, and the barrier component and the semiconductor component comprise a same material;
- a metal component, wherein at least a portion of the metal component is filled into a groove;
- and
- a planarization layer, wherein the planarization layer is disposed on the interlayer dielectric layer and covers the groove, and the pixel definition layer, the anode, the organic light emitting layer, the cathode, and the packaging layer are formed on the planarization layer in order;
- and
- wherein the first via hole and the second via hole are formed in the display area of the array substrate, a bottom of the first via hole and a bottom of the second via hole are connected to the semiconductor component, the groove is formed in the bending area of the array substrate, and the barrier component is formed in the bending area, and
- wherein the groove comprises a first groove and a second groove, an opening of the second groove is formed at a bottom of the first groove, and the barrier component is formed at a bottom of the first groove and exposes the opening of the second groove.
13 more elements
Dependencies are inferred from the claim text.