Memory device and manufacturing method thereof

A method, comprising:

• forming a dielectric layer over a wafer;
• forming a bottom via opening and a trench in the dielectric layer;
• forming a bottom electrode via in the bottom via opening;
• sequentially forming a bottom electrode layer, a memory material layer, and a top electrode layer over the dielectric layer and in the trench;
• forming a patterned mask over the top electrode layer by using a portion of the top electrode layer in the trench as an alignment mark;
• and
• sequentially patterning the top electrode layer, the memory material layer, and the bottom electrode layer by using the patterned mask as an etching mask, wherein patterning the bottom electrode layer is such that the dielectric layer is exposed through the trench.

A method comprising:

• forming a bottom electrode layer over a bottom electrode via and a trench in a first dielectric layer on a wafer;
• sequentially forming a memory material layer and a top electrode layer over the bottom electrode layer;
• forming a patterned mask over the top electrode layer by using a portion of the top electrode layer in the trench as an alignment mark;
• patterning the top electrode layer, the memory material layer, and the bottom electrode layer by using the patterned mask as an etching mask;
• and
• forming a spacer structure in contact with sidewalls of the bottom electrode layer and the memory material layer in the trench.