Ferroelectric tunnel junction memory device using a magnesium oxide tunneling dielectric and methods for forming the same

A method of forming a ferroelectric tunnel junction (FTJ) memory array, the method comprising:

• forming an array of transistors located on, or over, a substrate;
• and
• forming a layer stack including a bottom electrode material layer, ferroelectric tunnel junction material layers, and a top electrode material layer over a substrate prior to, or after, formation of the array of transistors, wherein the ferroelectric tunnel junction material layers comprise at least one ferroelectric material layer and at least one tunneling dielectric layer;
• and
• patterning the layer stack into a two-dimensional array of ferroelectric tunnel junction memory cells;
• and
• providing electrical connections between the array of transistors and the two-dimensional array of ferroelectric tunnel junction memory cells such that each of the transistors comprises an access transistor for a respective one ferroelectric tunnel junction memory cell within the two-dimensional array of ferroelectric tunnel junction memory cells.