Block-to-block isolation and deep contact using pillars in a memory array

An integrated circuit memory comprising:

• a first memory block;
• a second memory block;
• a plurality of Word Lines (WLs) including a first WL and a second WL;
• a plurality of pillars including a dummy pillar and a memory pillar, the dummy pillar and memory pillars each extending through both the first and second WLs, wherein the dummy pillar is (i) electrically isolated from the first WL by a first isolation layer that extends on a first plane along a periphery of the dummy pillar, and (ii) electrically isolated from the second WL by a second isolation layer that extends on a second plane along the periphery of the dummy pillar, wherein the dummy pillar is included in a slit area between the first memory block and the second memory block;
• a first memory cell at a junction of the memory pillar and the first WL;
• and
• a second memory cell at a junction of the memory pillar and the second WL, wherein each of the dummy pillar and the memory pillar comprises:
• a pillar core;
• a dielectric layer around at least a section of the pillar core;
• a floating gate layer around at least a section of the dielectric layer;
• and
• two or more inter-poly dielectric (IPD) layers around at least a section of the floating gate layer.

A method to form an integrated flash memory structure, the method comprising:

• forming a first trench, a second trench, and a third trench that extend through a plurality of Word Lines (WLs);
• depositing a liner on sidewalls of the first trench, without depositing any liner on sidewalls of the second and third trenches;
• forming, through each of the second trench and the third trench, recesses within the WLs that abut the second and third trenches;
• depositing electrically isolating material within the recesses;
• removing the liner from the sidewalls of the first trench;
• and
• forming a first pillar in the first trench, a second pillar in the second trench, and a third pillar in the third trench, wherein forming the first, second, and third pillars includes:
• forming the first, second, and third pillars such that each of the first, second, and third pillars comprise (i) a pillar core, (ii) a dielectric layer around at least a section of the pillar core, (iii) a floating gate layer around at least a section of the dielectric layer, and (iv) two or more inter-poly dielectric (IPD) layers around at least a section of the floating gate layer.