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US 12,120,868 B2Granted
Semiconductor device with buried bit line and preparation method thereof
AssigneeChangxin Memory Technologies, Inc.
InventorsRan Li, Xing Jin, Ming Cheng
Life of this patent
Estimating the term…
Abstract
A semiconductor device with a buried bit line and a preparation method thereof are provided. The preparation method of a semiconductor device with a buried bit line includes: providing a substrate; forming bit line trenches; forming a bit line structure in the bit line trench; and forming word line structures in the substrate. The semiconductor device with a buried bit line includes a substrate, bit line trenches, a bit line structure, and word line structures.
Claims13
A preparation method of a semiconductor device with a buried bit line, comprising:
- providing a substrate, and forming, in the substrate, a plurality of active regions defined by an isolation structure, wherein each of the active regions extends along a first direction;
- forming bit line trenches, wherein each of the bit line trenches extends along a second direction, each of the bit line trenches sequentially passes through the active region and the isolation structure in an S-shaped trend, and the second direction forms an acute angle with the first direction;
- forming a bit line structure in each of the bit line trenches, wherein the bit line structure comprises a bit line formed at a bottom of each of the bit line trenches and an isolation layer covering the bit line;
- and
- forming word line structures in the substrate, wherein each of the word line structures extends along a third direction and sequentially passes through the active region and the isolation structure, the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structure, and in the active region, the bit line and the word line structure are disposed at intervals;
- wherein a depth of each of the word line structures passing through the isolation structure is less than a depth of each of the word line structures passing through the active region.
3 more elements
A semiconductor device with a buried bit line, comprising:
- a substrate, wherein the substrate is provided with a plurality of active regions defined by an isolation structure, and each of the active regions extends along a first direction;
- bit line trenches, extending along a second direction, wherein each of the bit line trenches sequentially passes through the active region and the isolation structure in an S-shaped trend, and the second direction forms an acute angle with the first direction;
- a bit line structure, comprising a bit line and an isolation layer, wherein the bit line is formed in the each of bit line trenches, and the isolation layer covers the bit line and fills the bit line trenches;
- and
- word line structures, extending along a third direction, and sequentially passing through the active region and the isolation structure, wherein the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structures, and in the active region, the bit line and the word line structure are disposed at intervals;
- wherein a depth of each of the word line structures passing through the isolation structure is less than a depth of each of the word line structures passing through the active region.
3 more elements
A semiconductor device with a buried bit line, comprising:
- a substrate, wherein the substrate is provided with a plurality of active regions defined by an isolation structure, and each of the active regions extends along a first direction;
- bit line trenches, extending along a second direction, wherein each of the bit line trenches sequentially passes through the active region and the isolation structure in an S-shaped trend, and the second direction forms an acute angle with the first direction:
- a bit line structure, comprising a bit line and an isolation layer, wherein the bit line is formed in the each of bit line trenches, and the isolation layer covers the bit line and fills the bit line trenches;
- and
- word line structures, extending along a third direction, and sequentially passing through the active region and the isolation structure, wherein the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structures, and in the active region, the bit line and the word line structure are disposed at intervals:
- wherein
- a width of each of the bit line trenches is less than a width of each of the bit-line primary trenches.
4 more elements
Dependencies are inferred from the claim text.