Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure

A computer system, comprising:

• a power supply;
• and
• an IC die coupled to the power supply, wherein the IC die comprises:
• an array of memory cells, wherein individual ones of the memory cells comprise:
• a stacked field effect transistor structure, comprising:
• a stack of channel regions comprising a semiconductor material;
• one or more gate electrodes around the stack of channel regions;
• and
• a stack of source and drain regions comprising a first pair of source and drain regions electrically coupled to a first of the channel regions and over a second pair of source and drain regions electrically coupled to a second of the channel regions;
• a first capacitor comprising a metal-insulator-metal (MIM) structure on a first side of the stacked transistor structure, wherein the first capacitor comprises a first terminal that is electrically coupled to a first of the first pair of source and drain regions;
• and
• a second capacitor comprising a MIM structure on a second side of the stacked transistor structure, opposite the first side, wherein the second capacitor comprises a terminal that is electrically coupled to a first of the second pair of source and drain regions.

A method of fabricating an IC comprising an array of memory cells, the method comprising:

• receiving a workpiece comprising a plurality of transistor stack structures, wherein individual ones of the transistor stack structures comprise:
• a stack of channel regions comprising a semiconductor material;
• one or more gate electrodes around the stack of channel regions;
• and
• a stack of source and drain regions comprising a first pair of source and drain regions electrically coupled to a first of the channel regions, and over a second pair of source and drain regions electrically coupled to a second of the channel regions;
• forming a plurality of first capacitors on a first side of the transistor stack structures, wherein individual ones of the first capacitors are electrically coupled to a first of the first pair of source and drain regions in corresponding individual ones of the transistor stack structures;
• forming, on the first side of the transistor stack structures, cell addressing interconnects to one or more first terminals of each of the transistor stack structures;
• forming a plurality of second capacitors on a second side of the transistor stack structures, wherein individual ones of the second capacitors are electrically coupled to a first of the second pair of source and drain regions in corresponding individual ones of the transistor stack structures;
• and
• forming, on the second side of the transistor stack structures, cell addressing interconnects to one or more second terminals of each of the transistor stack structures.