A memory device using a semiconductor element in which a page is composed of a plurality of memory cells arrayed on a substrate in a row direction, and a plurality of pages are arrayed in a column direction,
- each of the memory cells included in each of the pages comprising:
- a semiconductor base standing on the substrate in a vertical direction relative to the substrate or extending on the substrate in a horizontal direction relative to the substrate;
- a first impurity layer and a second impurity layer at two ends of the semiconductor base;
- a first gate insulating layer surrounding a portion or all of a side surface of the semiconductor base between the first impurity layer and the second impurity layer, the first gate insulating layer being in contact with or proximate to the first impurity layer;
- a second gate insulating layer surrounding the side surface of the semiconductor base, being connected to the first gate insulating layer, and being in contact with or proximate to the second impurity layer;
- a first gate conductor layer and a second gate conductor layer covering two opposite side surfaces of the first gate insulating layer while being separate from each other;
- a third gate conductor layer covering the second gate insulating layer;
- and
- a channel semiconductor layer of the semiconductor base covered with the first gate insulating layer and the second gate insulating layer, wherein:
- a voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer is controlled to form a hole group by impact ionization inside the channel semiconductor layer, and the hole group is held;
- in a page write operation, a voltage of the channel semiconductor layer is set to a first data holding voltage that is higher than a voltage of one or both of the first impurity layer and the second impurity layer;
- in a page erase operation, a voltage applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is controlled to extract the hole group from one or both of the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is set to a second data holding voltage that is lower than the first data holding voltage;
- of the memory cell, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first plate line, the second gate conductor layer is connected to a second plate line, and the third gate conductor layer is connected to a word line;
- in the page erase operation, the hole group in the channel semiconductor layer is extracted from one or both of the first impurity layer and the second impurity layer by lowering the second plate line from a first voltage to a second voltage at a first time, raising the first plate line from a third voltage to a fourth voltage and raising a voltage of the word line from a fifth voltage to a sixth voltage at a second time, and returning the second plate line from the second voltage to the first voltage at a third time;
- and
- the voltage of the channel semiconductor layer, to which the first plate line and the word line are capacitively coupled, is lowered to the second data holding voltage by returning the first plate line from the fourth voltage to the third voltage and returning the voltage of the word line from the sixth voltage to the fifth voltage at a fourth time.