Signal processing device, and image display device comprising same

An image display apparatus comprising:

• a display;
• and
• a signal processing device,
• wherein the signal processing device comprises:
• an equalizer configured to receive an input signal through a channel and equalize the received input signal;
• and
• a control circuit configured to determine an equalizer control code in response to a first signal output from the equalizer and output the determined equalizer control code to the equalizer,
• wherein the equalizer equalizes the received input signal based on the equalizer control code, and
• wherein, in response to the first signal comprising a clock pattern signal including a first pattern signal and a second pattern signal, the control circuit applies an offset voltage to the first pattern signal and measures the magnitude of the clock pattern signal based on a difference value between the second pattern signal and the first pattern signal to which the offset voltage is applied.