100BASE-TX transceiver with transmit clock selected from output clock of clock generator circuit and receive recovered clock of clock and data recovery circuit and associated method

A 100BASE-TX transceiver comprising:

• a receive (RX) circuit, arranged to receive an input data to generate an RX data;
• a transmit (TX) circuit, arranged to transmit a TX data according to a TX clock, to generate an output data;
• a clock generator circuit, arranged to generate an output clock;
• a clock and data recovery (CDR) circuit, arranged to generate an RX recovered clock according to the RX data;
• a clock multiplexer circuit, arranged to receive the output clock and the RX recovered clock, and output the TX clock that is selected from the output clock and the RX recovered clock;
• and
• a decision logic, arranged to generate a local random number, obtain a random number from a link partner, and compare the local random number with the random number obtained from the link partner to set a selection control signal of the clock multiplexer circuit.

A 100BASE-TX transceiving method comprising:

• receiving an input data to generate a receive (RX) data;
• transmitting a transmit (TX) data according to a TX clock, to generate an output data;
• performing clock generation to generate an output clock;
• performing clock and data recovery (CDR) upon the RX data to generate an RX recovered clock;
• performing clock multiplexing upon the output clock and the RX recovered clock to output the TX clock that is selected from the output clock and the RX recovered clock;
• and
• checking a media independent interface (MDI) status that is set by an automatic media independent interface/media independent interface with crossover (MDI/MDIX) feature, and referring to the MDI status to configure the clock multiplexing.

A 100BASE-TX transceiving method comprising:

• receiving an input data to generate a receive (RX) data;
• transmitting a transmit (TX) data according to a TX clock, to generate an output data;
• performing clock generation to generate an output clock;
• performing clock and data recovery (CDR) upon the RX data to generate an RX recovered clock;
• performing clock multiplexing upon the output clock and the RX recovered clock to output the TX clock that is selected from the output clock and the RX recovered clock;
• and
• generating a local random number;
• obtaining a random number from a link partner;
• and
• comparing the local random number with the random number obtained from the link partner to configure the clock multiplexing.