Encoder and decoder

An entropy code decoder comprising:

• a register;
• a plurality of comparator circuits configured to compare cumulative distribution values corresponding to various values of data symbols with lower bits of a value stored in the register, respectively;
• a binary encoder circuit configured to output an output symbol as a decompressed data stream based on output values of the comparator circuits;
• and
• an arithmetic circuit configured to:
• obtain a first value corresponding to an appearance frequency of the output symbol and a second value corresponding to a cumulative distribution of the first value;
• calculate a third value through multiplication of the first value with a bit-shifted value of the value stored in the register and subtraction of the second value therefrom;
• and
• output a fourth value including at least a part of bits of the third value to update the value in the register to the fourth value.

A compression and decompression circuit comprising:

• an entropy code encoder comprising:
• a first register;
• a first arithmetic circuit configured to output, based on an input symbol, a first value corresponding to an appearance frequency of the input symbol and a second value corresponding to a cumulative distribution of the first value;
• a second arithmetic circuit configured to output a third value corresponding to division of a value of bits stored in the first register by the first value;
• a third arithmetic circuit configured to output a fourth value obtained by adding the second value to a bit-shifted value of the third value to the register, to update a value of bits stored in the first register to the fourth value;
• and
• a fourth arithmetic circuit configured to compare a value of upper bits stored in the first register and the first value and output lower bits of the value stored in the first register as a compressed data stream in accordance with a comparison result;
• and an entropy code decoder
• a second register;
• a plurality of comparator circuits configured to compare cumulative distribution values corresponding to various values of data symbols with a value of lower bits stored in the second register, respectively;
• a binary encoder circuit configured to output an output symbol as a decompressed data stream based on output values of the comparator circuits;
• and
• an arithmetic circuit configured to:
• obtain a fifth value corresponding to an appearance frequency of the output symbol and a sixth value corresponding to a cumulative distribution of the first value;
• calculate a seventh value through multiplication of the fifth value with a bit-shifted value of the value stored in the second register and subtraction of the sixth value therefrom;
• and
• output an eighth value including at least a part of bits of the seventh value to update the value in the second register to the eighth value.

An entropy code decoder comprising:

• a register;
• a plurality of comparator circuits configured to compare cumulative distribution values corresponding to various even values of data symbols with a value of lower bits stored in the register, respectively;
• a binary encoder circuit configured to output an output symbol as at least a part of a decompressed data stream based on output values of the comparator circuits;
• and
• an arithmetic circuit configured to:
• obtain a first value corresponding to an appearance frequency of the output symbol and a second value corresponding to an appearance frequency of the output symbol plus 1;
• calculate a third value through multiplication of the first value with a bit-shifted value of the value stored in the register and subtraction of a value corresponding to a cumulative distribution of the output symbol and a fourth value through multiplication of the second value with a bit-shifted value of the value stored in the register and subtraction of a value corresponding to a cumulative distribution of the output symbol plus 1;
• select one of the third value and the fourth value;
• and
• output a fifth value including at least a part of bits of the selected one of the third and fourth values to update the value in the register to the fifth value.