Ultra-low power instant lock phase lock loop (PLL)

A method for reducing a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit, the method comprising:

• receiving a reference signal having a reference frequency;
• setting a digitally controlled oscillator (DCO) to a target frequency that is greater, by a factor, than the reference frequency, the DCO generating an output signal, the target frequency is obtained from a calibration made using an open loop circuit configuration;
• using the output signal to generate a feedback signal;
• using a time-to-digital converter (TDC) to determine an initial phase difference between the reference signal and the feedback signal;
• and
• using a digital initial phase compensation circuit that adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.