Systems and methods for PLL gain calibration and duty cycle calibration using shared phase detector

A phase-locked loop (PLL), comprising:

• a phase detector configured to
• receive a delayed reference signal,
• receive a feedback signal, and
• output an error signal based on a first plurality of pulses of the delayed reference signal aligning with a second plurality of pulses of the feedback signal,
• gain calibration circuitry configured to
• receive the error signal,
• output an average value of the error signal, and
• adjust loop gain parameters or maintain the loop gain parameters of the PLL based on the average value of the error signal, and
• duty cycle calibration circuitry configured to
• receive the error signal,
• output the average value of the error signal, and
• output a duty cycle correction based on the average value of the error signal comprising a positive value or a negative value.

A method, comprising:

• receiving a reference signal at a time-to-digital converter (TDC) of a phase-locked loop (PLL);
• receiving a feedback signal at the TDC from feedback circuitry;
• and
• outputting, via the TDC, an error signal to gain calibration circuitry and duty cycle calibration circuitry based on whether a first plurality of pulses associated with the reference signal are aligned with a second plurality of pulses associated with the feedback signal.