Clock data recovery circuits and electronic systems that support data-based clock recovery

A clock data recovery circuit, comprising:

• a phase-locked loop configured to generate multiphase clock signals in response to a received clock signal;
• a phase interpolator configured to interpolate phases of the multiphase clock signals during generation of multiphase edge clock signals and multiphase sampling clock signals;
• and
• an edge clock adjust circuit configured to:
• (i) determine whether respective phases of the multiphase edge clock signals precede or lag behind a phase at which a data signal transitions, and (ii) adjust phases of some edge clock signals among the multiphase edge clock signals until determination results of all of the multiphase edge clock signals become the same, when determination results of the some edge clock signals are different from determination results of remaining edge clock signals.

An electronic system, comprising:

• a communication channel;
• a first device having a transmitter therein, which is configured to output a data signal to the communication channel;
• and
• a second device having a receiver therein, which is connected to the communication channel, said the receiver configured to:
• (i) recover, based on transition time points of the data signal, multiphase edge clock signals, (ii) adjust phases of the multiphase edge clock signals such that sampling time points of the multiphase edge clock signals have an equal interval therebetween, when sampling time points of some edge clock signals among the multiphase edge clock signals precede the transition time points and sampling time points of some of remaining edge clock signals lag behind the transition time points, (iii) sample the data signal with multiphase sampling clock signals having an intermediate phase of the multiphase edge clock signals, (iv) detect predetermined data patterns from the sampled data signal, and (v) adjust phases of the multiphase sampling clock signals according to a result of comparing, with each other, signal levels at sampling time points for sampling respective reference data symbols of the predetermined data patterns.